VAX MACRO and Instruction Set Reference Manual

Document revision date: 30 March 2001

VAX MACRO and Instruction Set Reference Manual

Contents

Index

9.2.1 Integer Arithmetic and Logical Instructions

The following instructions are described in this section:

Description and Opcode Number of Instructions

1. Add Aligned Word
ADAWI add.rw, sum.mw 1

2. Add 2 Operand
ADD{B,W,L}2 add.rx, sum.mx 3

3. Add 3 Operand
ADD{B,W,L}3 add1.rx, add2.rx, sum.wx 3

4. Add with Carry
ADWC add.rl, sum.ml 1

5. Arithmetic Shift
ASH{L,Q} cnt.rb, src.rx, dst.wx 2

6. Bit Clear 2 Operand
BIC{B,W,L}2 mask.rx, dst.mx 3

7. Bit Clear 3 Operand
BIC{B,W,L}3 mask.rx, src.rx, dst.wx 3

8. Bit Set 2 Operand
BIS{B,W,L}2 mask.rx, dst.mx 3

9. Bit Set 3 Operand
BIS{B,W,L}3 mask.rx, src.rx, dst.wx 3

10. Bit Test
BIT{B,W,L} mask.rx, src.rx 3

11. Clear
CLR{B,W,L,Q,O} dst.wx 5

12. Compare
CMP{B,W,L} src1.rx, src2.rx 3

13. Convert
CVT{B,W,L}{B,W,L} src.rx, dst.wy
All pairs except BB,WW,LL 6

14. Decrement
DEC{B,W,L} dif.mx 3

15. Divide 2 Operand
DIV{B,W,L}2 divr.rx, quo.mx 3

16. Divide 3 Operand
DIV{B,W,L}3 divr.rx, divd.rx, quo.wx 3

17. Extended Divide
EDIV divr.rl, divd.rq, quo.wl, rem.wl 1

18. Extended Multiply
EMUL mulr.rl, muld.rl, add.rl, prod.wq 1

19. Increment
INC{B,W,L} sum.mx 3

20. Move Complemented
MCOM{B,W,L} src.rx, dst.wx 3

21. Move Negated
MNEG{B,W,L} src.rx, dst.wx 3

22. Move
OV{B,W,L,Q} src.rx, dst.wx 4

23. Move Zero-Extended
MOVZ{BW,BL,WL} src.rx, dst.wy 3

24. Multiply 2 Operand
MUL{B,W,L}2 mulr.rx, prod.mx 3

25. Multiply 3 Operand
MUL{B,W,L}3 mulr.rx, muld.rx, prod.wx 3

26. Push Long
PUSHL src.rl, {-(SP).wl} 1

27. Rotate Long
ROTL cnt.rb, src.rl, dst.wl 1

28. Subtract with Carry
SBWC sub.rl, dif.ml 1

29. Subtract 2 Operand
SUB{B,W,L}2 sub.rx, dif.mx 3

30. Subtract 3 Operand
SUB{B,W,L}3 sub.rx, min.rx, dif.wx 3

31. Test
TST{B,W,L} src.rx 3

32. Exclusive OR 2 Operand
XOR{B,W,L}2 mask.rx, dst.mx 3

33. Exclusive OR 3 Operand
XOR{B,W,L}3 mask.rx, src.rx, dst.wx 3

	Description and Opcode	Number of Instructions
1.	Add Aligned Word ADAWI add.rw, sum.mw	1
2.	Add 2 Operand ADD{B,W,L}2 add.rx, sum.mx	3
3.	Add 3 Operand ADD{B,W,L}3 add1.rx, add2.rx, sum.wx	3
4.	Add with Carry ADWC add.rl, sum.ml	1
5.	Arithmetic Shift ASH{L,Q} cnt.rb, src.rx, dst.wx	2
6.	Bit Clear 2 Operand BIC{B,W,L}2 mask.rx, dst.mx	3
7.	Bit Clear 3 Operand BIC{B,W,L}3 mask.rx, src.rx, dst.wx	3
8.	Bit Set 2 Operand BIS{B,W,L}2 mask.rx, dst.mx	3
9.	Bit Set 3 Operand BIS{B,W,L}3 mask.rx, src.rx, dst.wx	3
10.	Bit Test BIT{B,W,L} mask.rx, src.rx	3
11.	Clear CLR{B,W,L,Q,O} dst.wx	5
12.	Compare CMP{B,W,L} src1.rx, src2.rx	3
13.	Convert CVT{B,W,L}{B,W,L} src.rx, dst.wy All pairs except BB,WW,LL	6
14.	Decrement DEC{B,W,L} dif.mx	3
15.	Divide 2 Operand DIV{B,W,L}2 divr.rx, quo.mx	3
16.	Divide 3 Operand DIV{B,W,L}3 divr.rx, divd.rx, quo.wx	3
17.	Extended Divide EDIV divr.rl, divd.rq, quo.wl, rem.wl	1
18.	Extended Multiply EMUL mulr.rl, muld.rl, add.rl, prod.wq	1
19.	Increment INC{B,W,L} sum.mx	3
20.	Move Complemented MCOM{B,W,L} src.rx, dst.wx	3
21.	Move Negated MNEG{B,W,L} src.rx, dst.wx	3
22.	Move OV{B,W,L,Q} src.rx, dst.wx	4
23.	Move Zero-Extended MOVZ{BW,BL,WL} src.rx, dst.wy	3
24.	Multiply 2 Operand MUL{B,W,L}2 mulr.rx, prod.mx	3
25.	Multiply 3 Operand MUL{B,W,L}3 mulr.rx, muld.rx, prod.wx	3
26.	Push Long PUSHL src.rl, {-(SP).wl}	1
27.	Rotate Long ROTL cnt.rb, src.rl, dst.wl	1
28.	Subtract with Carry SBWC sub.rl, dif.ml	1
29.	Subtract 2 Operand SUB{B,W,L}2 sub.rx, dif.mx	3
30.	Subtract 3 Operand SUB{B,W,L}3 sub.rx, min.rx, dif.wx	3
31.	Test TST{B,W,L} src.rx	3
32.	Exclusive OR 2 Operand XOR{B,W,L}2 mask.rx, dst.mx	3
33.	Exclusive OR 3 Operand XOR{B,W,L}3 mask.rx, src.rx, dst.wx	3

ADAWI

Add Aligned Word Interlocked

Format

opcode add.rw, sum.mw

Condition Codes

N\|\| <--- sum LSS 0;
Z\|\| <--- sum EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- {carry from most-significant bit};

Exceptions

reserved operand fault
integer overflow

Opcodes

ADAWI

Add Aligned Word Interlocked

Description

The addend operand is added to the sum operand, and the sum operand is replaced by the result. If the sum operand is contained in memory, then the operation is interlocked against interlocked operations to the same address from other processors. The destination must be aligned on a word boundary; that is, bit 0 of the address of the sum operand must be zero. If it is not, a reserved operand fault is taken.

Notes

Integer overflow occurs if the input operands to the add have the same sign, and the result has the opposite sign. On overflow, the sum operand is replaced by the low-order bits of the true result.
If the addend and the sum operands overlap, the result and the condition codes are UNPREDICTABLE.

ADD

Add

Format

2operand: opcode add.rx, sum.mx
3operand: opcode add1.rx, add2.rx, sum.wx

Condition Codes

N\|\| <--- sum LSS 0;
Z\|\| <--- sum EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- {carry from most-significant bit};

Exceptions

integer overflow

Opcodes

80	ADDB2	Add Byte 2 Operand
81	ADDB3	Add Byte 3 Operand
A0	ADDW2	Add Word 2 Operand
A1	ADDW3	Add Word 3 Operand
C0	ADDL2	Add Long 2 Operand
C1	ADDL3	Add Long 3 Operand

Description

In 2 operand format, the addend operand is added to the sum operand and the sum operand is replaced by the result. In 3 operand format, the addend 1 operand is added to the addend 2 operand and the sum operand is replaced by the result.

Note

Integer overflow occurs if the input operands to the add have the same sign and the result has the opposite sign. On overflow, the sum operand is replaced by the low-order bits of the true result.

ADWC

Add with Carry

Format

opcode add.rl, sum.ml

Condition Codes

N\|\| <--- sum LSS 0;
Z\|\| <--- sum EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- {carry from most-significant bit};

Exceptions

integer overflow

Opcodes

ADWC

Add with Carry

Description

The contents of the condition code C-bit and the addend operand are added to the sum operand and the sum operand is replaced by the result.

Notes

On overflow, the sum operand is replaced by the low-order bits of the true result.
The two additions in the operation are performed simultaneously.

ASH

Arithmetic Shift

Format

opcode cnt.rb, src.rx, dst.wx

Condition Codes

N\|\| <--- dst LSS 0;
Z\|\| <--- dst EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- 0;

Exceptions

integer overflow

Opcodes

78	ASHL	Arithmetic Shift Long
79	ASHQ	Arithmetic Shift Quad

Description

The source operand is arithmetically shifted by the number of bits specified by the count operand and the destination operand is replaced by the result. The source operand is unaffected. A positive count operand shifts to the left, bringing zeros into the least significant bit. A negative count operand shifts to the right, bringing in copies of the most significant (sign) bit into the most significant bit. A zero count operand replaces the destination operand with the unshifted source operand.

Notes

Integer overflow occurs on a left shift if any bit shifted into the sign bit position differs from the sign bit of the source operand.
If cnt GTR 32 (ASHL) or cnt GTR 64 (ASHQ), the destination operand is replaced by zero.
If cnt LEQ -31 (ASHL) or cnt LEQ -63 (ASHQ), all the bits of the destination operand are copies of the sign bit of the source operand.

BIC

Bit Clear

Format

2operand: opcode mask.rx, dst.mx
3operand: opcode mask.rx, src.rx, dst.wx

Condition Codes

N\|\| <--- dst LSS 0;
Z\|\| <--- dst EQL 0;
V\|\| <--- 0;
C\|\| <--- C;

Exceptions

None.

Opcodes

8A	BICB2	Bit Clear Byte
8B	BICB3	Bit Clear Byte
AA	BICW2	Bit Clear Word
AB	BICW3	Bit Clear Word
CA	BICL2	Bit Clear Long
CB	BICL3	Bit Clear Long

Description

In 2 operand format, the result of the logical AND on the destination operand and the one's complement of the mask operand replaces the destination operand. In 3 operand format, the result of the logical AND on the source operand and the one's complement of the mask operand replaces the destination operand.

BIS

Bit Set

Format

2operand: opcode mask.rx, dst.mx
3operand: opcode mask.rx, src.rx, dst.wx

Condition Codes

N\|\| <--- dst LSS 0;
Z\|\| <--- dst EQL 0;
V\|\| <--- 0;
C\|\| <--- C;

Exceptions

None.

Opcodes

88	BISB2	Bit Set Byte 2 Operand
89	BISB3	Bit Set Byte 3 Operand
A8	BISW2	Bit Set Word 2 Operand
A9	BISW3	Bit Set Word 3 Operand
C8	BISL2	Bit Set Long 2 Operand
C9	BISL3	Bit Set Long 3 Operand

Description

In 2 operand format, the result of the logical OR on the mask operand and the destination operand replaces the destination operand. In 3 operand format, the result of the logical OR on the mask operand and the source operand replaces the destination operand.

BIT

Bit Test

Format

opcode mask.rx, src.rx

Condition Codes

N\|\| <--- tmp LSS 0;
Z\|\| <--- tmp EQL 0;
V\|\| <--- 0;
C\|\| <--- C;

Exceptions

None.

Opcodes

93	BITB	Bit Test Byte
B3	BITW	Bit Test Word
D3	BITL	Bit Test Long

Description

The logical AND is performed on the mask operand and the source operand. Both operands are unaffected. The only action is to modify condition codes.

CLR

Clear

Format

opcode dst.wx

Condition Codes

N\|\| <--- 0;
Z\|\| <--- 1;
V\|\| <--- 0;
C\|\| <--- C;

Exceptions

None.

Opcodes

94	CLRB	Clear Byte
B4	CLRW	Clear Word
D4	CLRL	Clear Long
7C	CLRQ	Clear Quad
7CFD	CLRO	Clear Octa

Description

The destination operand is replaced by zero.

Note

CLRx dst is equivalent to MOVx S^#0, dst, but is 1 byte shorter.

CMP

Compare

Format

opcode src1.rx, src2.rx

Condition Codes

N\|\| <--- src1 LSS src2;
Z\|\| <--- src1 EQL src2;
V\|\| <--- 0;
C\|\| <--- src1 LSSU src2;

Exceptions

None.

Opcodes

91	CMPB	Compare Byte
B1	CMPW	Compare Word
D1	CMPL	Compare Long

Description

The source 1 operand is compared with the source 2 operand. The only action is to modify the condition codes.

CVT

Convert

Format

opcode src.rx, dst.wy

Condition Codes

N\|\| <--- dst LSS 0;
Z\|\| <--- dst EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- 0;

Exceptions

integer overflow

Opcodes

99	CVTBW	Convert Byte to Word
98	CVTBL	Convert Byte to Long
33	CVTWB	Convert Word to Byte
32	CVTWL	Convert Word to Long
F6	CVTLB	Convert Long to Byte
F7	CVTLW	Convert Long to Word

Description

The source operand is converted to the data type of the destination operand and the destination operand is replaced by the result. Conversion of a shorter data type to a longer one is done by sign extension; conversion of longer data type to a shorter one is done by truncation of the higher-numbered (most significant) bits.

Note

Integer overflow occurs if any truncated bits of the source operand are not equal to the sign bit of the destination operand.

Contents

Index

privacy and legal statement

4515PRO_016.HTML

N\|\| <--- sum LSS 0;
Z\|\| <--- sum EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- {carry from most-significant bit};

N\|\| <--- sum LSS 0;
Z\|\| <--- sum EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- {carry from most-significant bit};

N\|\| <--- sum LSS 0;
Z\|\| <--- sum EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- {carry from most-significant bit};

N\|\| <--- dst LSS 0;
Z\|\| <--- dst EQL 0;
V\|\| <--- {integer overflow};
C\|\| <--- 0;

N\|\| <--- dst LSS 0;
Z\|\| <--- dst EQL 0;
V\|\| <--- 0;
C\|\| <--- C;