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| Document revision date: 30 March 2001 | |
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There are alignment, stride, address specifier context, and access mode
considerations for the vector memory access instructions.
10.10.1 Alignment Considerations
Vector memory access instructions require their vector operands to be naturally aligned in memory. Longwords must be aligned on longword boundaries. Quadwords must be aligned on quadword boundaries. If any vector element is not naturally aligned in memory, an access control violation occurs. For further details, see Section 10.6.1, Vector Memory Management Exception Handling.
The scalar operands need not be naturally aligned in memory.
10.10.2 Stride Considerations
A vector's stride is defined as the number of memory locations (bytes)
between the starting address of consecutive vector elements. A
contiguous vector that has longword elements has a stride of four; a
contiguous vector that has quadword elements has a stride of eight.
10.10.3 Context of Address Specifiers
The base address specifier used by the vector memory access
instructions is of byte context, regardless of the data type. Arrays
are addressed as byte strings. Index values in array specifiers are
multiplied by one, and the amount of autoincrement or autodecrement,
when either of these modes is used, is one.
10.10.4 Access Mode
A vector memory access instruction is executed using the access mode in
effect when the instruction is issued by the scalar processor.
10.10.5 Memory Instructions
This section describes VAX vector architecture memory instructions.
Load Memory Data into Vector Register
VLDL [/M[0|1]] base, stride, VcArchitectureVLDQ [/M[0|1]] base, stride, Vc
opcode cntrl.rw, base.ab, stride.rl
| 34FD | VLDL | Load Longword Vector from Memory to Vector Register |
| 36FD | VLDQ | Load Quadword Vector from Memory to Vector Register |
access control violation
translation not valid
vector alignment
The source operand vector is fetched from memory and is written to vector destination register Vc. The length of the vector is specified by VLR. The virtual address of the source vector is computed using the base address and the stride. The address of element i (0 LEQU i LEQU (VLR-1)) is computed as {base+{i*stride}}. The stride can be positive, negative, or zero.In VLDL, bits <31:0> of each destination vector element receive the memory data and bits <63:32> are UNPREDICTABLE.
If any vector element operated upon is not naturally aligned in memory, a vector alignment exception occurs.
The results of VLD are unaffected by the setting of cntrl<MI>. For more details about the use of cntrl<MI>, see Section 10.3.3, Modify Intent bit.
If the addressing mode of the BASE operand is immediate, the results of the instruction are UNPREDICTABLE.
An implementation may load the elements of the vector in any order, and more than once. When a vector processor memory management exception occurs, the contents of the destination vector elements are UNPREDICTABLE.
Gather Memory Data into Vector Register
VGATHL [/M[0|1]] base, Vb, VcArchitectureVGATHQ [/M[0|1]] base, Vb, Vc
opcode cntrl.rw, base.ab
| 35FD | VGATHL | Gather Longword Vector from Memory to Vector Register |
| 37FD | VGATHQ | Gather Quadword Vector from Memory to Vector Register |
access control violation
translation not valid
vector alignment
The source operand vector is fetched from memory and is written to vector destination register Vc. The length of the vector is specified by VLR. The virtual address of the vector is computed using the base address and the 32-bit offsets in vector register Vb. The address of element i (0 LEQU i LEQU (VLR-1)) is computed as {base+Vb[i]}. The 32-bit offset can be positive, negative, or zero.In VGATHL, bits <31:0> of each destination vector element receive the memory data and bits <63:32> are UNPREDICTABLE.
If any vector element operated upon is not naturally aligned in memory, a vector alignment exception occurs.
The results of VGATH are unaffected by the setting of cntrl<MI>. For more details about the use of cntrl<MI>, see Section 10.3.3, Modify Intent bit.
If the addressing mode of the BASE operand is immediate, the results of the instruction are UNPREDICTABLE.
An implementation may load the elements of the vector in any order, and more than once. When a vector processor memory management exception occurs, the contents of the destination vector elements are UNPREDICTABLE.
If the same vector register is used as both source and destination, the result of the VGATH is UNPREDICTABLE.
Store Vector Register Data into Memory
VSTL [/0|1] Vc, base, strideArchitectureVSTQ [/0|1] Vc, base, stride
opcode cntrl.rw, base.ab, stride.rl
| 9CFD | VSTL | Store Longword Vector from Vector Register to Memory |
| 9EFD | VSTQ | Store Quadword Vector from Vector Register to Memory |
access control violation
translation not valid
vector alignment
modify
The source operand in vector register Vc is written to memory. The length of the vector is specified by the Vector Length Register (VLR). The virtual address of the destination vector is computed using the base address and the stride. The address of element i (0 LEQU i LEQU (VLR-1)) is computed as {base+{i*stride}}. The stride can be positive, negative, or zero.If any vector element operated upon is not naturally aligned in memory, a vector alignment exception occurs.
For a nonzero stride value, an implementation may store the vector elements in parallel; therefore the order in which these elements are stored is UNPREDICTABLE. Furthermore, if the nonzero stride causes result locations in memory to overlap, then the values stored in the overlapping result locations are also UNPREDICTABLE.
For a stride value of zero, the highest numbered register element destined for the single memory location becomes the final value of that location.
When a vector processor memory management exception occurs, it is UNPREDICTABLE whether the vector processor writes any result location for which an exception did not occur. If the fault condition can be eliminated by software and the instruction restarted, then the vector processor will ensure that all destination locations are written.
If the destination vector overlaps the vector instruction control word, base, or stride operand, the result of the instruction is UNPREDICTABLE.
If the addressing mode of the BASE operand is immediate, the results of the instruction are UNPREDICTABLE.
Scatter Vector Register Data into Memory
VSCATL [/0|1] Vc, base, VbArchitectureVSCATQ [/0|1] Vc, base, Vb
opcode cntrl.rw, base.ab
| 9DFD | VSCATL | Scatter Longword Vector from Vector Register to Memory |
| 9FFD | VSCATQ | Scatter Quadword Vector from Vector Register to Memory |
access control violation
translation not valid
vector alignment
modify
The source vector operand Vc is written to memory. The length of the vector is specified by the Vector Length Register (VLR) register. The virtual address of the destination vector is computed using the base address operand and the 32-bit offsets in vector register Vb. The address of element i (0 LEQU i LEQU (VLR-1)) is computed as {base+Vb[i]}. The 32-bit offset can be positive, negative, or zero.If any vector element operated upon is not naturally aligned in memory, a vector alignment exception occurs.
An implementation may store the vector elements in parallel; therefore, the order in which elements are stored to different memory locations is UNPREDICTABLE. In the case where multiple elements are destined for the same memory location, the highest numbered element among them becomes the final value of that location.
When a vector processor memory management exception occurs, it is UNPREDICTABLE whether the vector processor writes any result location for which an exception did not occur. If the fault condition can be eliminated by software and the instruction restarted, then the vector processor will ensure that all destination locations are written.
If the destination vector overlaps the vector instruction control word or base operand, the result of the instruction is UNPREDICTABLE.
If the addressing mode of the BASE operand is immediate, the results of the instruction are UNPREDICTABLE.
This section describes VAX vector architecture integer instructions.
Vector Integer Add
vector + vector:ArchitectureVVADDL [/0|1] Va, Vb, Vc
scalar + vector:
VSADDL [/0|1] scalar, Vb, Vc
vector + vector: opcode cntrl.rw
scalar + vector: opcode cntrl.rw, addend.rl
| 80FD | VVADDL | Vector Vector Add Longword |
| 81FD | VSADDL | Vector Scalar Add Longword |
integer overflow
The scalar addend or Va operand is added, elementwise, to vector register Vb and the 32-bit sum is written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).If integer overflow is detected and cntrl<EXC> is set, the exception type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete. On integer overflow, the low-order 32 bits of the true result are stored in the destination element.
Vector Integer Compare
vector--vector:Architecture
{VVGTRL | VVEQLL |VVLSSL |VVLEQL|VVNEQL|VVGEQL} [/0|1] Va, Vbscalar--vector:
{VSGTRL|VSEQLL|VSLSSL|VSLEQL|VSNEQL|VSGEQL} [/0|1] src, Vb
vector--vector: opcode cntrl.rw
scalar--vector: opcode cntrl.rw, src.rl
| C0FD | VVCMPL | Vector Vector Compare Longword |
| C1FD | VSCMPL | Vector Scalar Compare Longword |
The condition being tested is determined by cntrl<2:0>, as follows:
| Value of cntrl<2:0> | Meaning |
|---|---|
| 0 | Greater than |
| 1 | Equal |
| 2 | Less than |
| 3 | Reserved 1 |
| 4 | Less than or equal |
| 5 | Not equal |
| 6 | Greater than or equal |
| 7 | Reserved 1 |
The scalar or Va operand is compared, elementwise, with vector register Vb. The length of the vector is specified by the Vector Length Register (VLR). For each element comparison, if the specified relationship is true, the Vector Mask Register bit (VMR<i>) corresponding to the vector element is set to one; otherwise, it is cleared. If cntrl<MOE> is set, VMR bits corresponding to elements that do not match cntrl<MTF> are left unchanged. VMR bits beyond the vector length are left unchanged. Only bits <31:0> of each vector element participate in the operation.
Vector Integer Multiply
vector * vector:ArchitectureVVMULL [/V[0|1]] Va, Vb, Vc
scalar * vector:
VSMULL [/V[0|1]] scalar, Vb, Vc
vector * vector: opcode cntrl.rw
scalar * vector: opcode cntrl.rw, mulr.rl
| A0FD | VVMULL | Vector Vector Multiply Longword |
| A1FD | VSMULL | Vector Scalar Multiply Longword |
integer overflow
The scalar multiplier or vector operand Va is multiplied, elementwise, by vector operand Vb and the least significant 32 bits of the signed 64-bit product are written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).If integer overflow is detected and cntrl<EXC> is set, the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete. On integer overflow, the low-order 32 bits of the true result are stored in the destination element.
Vector Integer Subtract
vector--vector:ArchitectureVVSUBL [/V[0|1]] Va, Vb, Vc
scalar--vector:
VSSUBL [/V[0|1]] scalar, Vb, Vc
vector--vector: opcode cntrl.rw
scalar--vector: opcode cntrl.rw, min.rl
| 88FD | VVSUBL | Vector Vector Subtract Longword |
| 89FD | VSSUBL | Vector Scalar Subtract Longword |
integer overflow
The vector operand Vb is subtracted, elementwise, from the scalar minuend or vector operand Va. The 32-bit difference is written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).If integer overflow is detected and cntrl<EXC> is set, the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete. On integer overflow, the low-order 32 bits of the true result are stored in the destination element.
This section describes VAX vector architecture logical and shift instructions.
Vector Logical Functions
vector op vector:Architecture
{VVBISL|VVXORL|VVBICL} [/V[0|1]] Va, Vb, Vcvector op scalar:
{VSBISL|VSXORL|VSBICL} [/V[0|1]] scalar, Vb, Vc
op vector: opcode cntrl.rw
op scalar: opcode cntrl.rw, src.rl
| C8FD | VVBISL | Vector Vector Bit Set Longword |
| E8FD | VVXORL | Vector Vector Exclusive-OR Longword |
| CCFD | VVBICL | Vector Vector Bit Clear Longword |
| C9FD | VSBISL | Vector Scalar Bit Set Longword |
| E9FD | VSXORL | Vector Scalar Exclusive-OR Longword |
| CDFD | VSBICL | Vector Scalar Bit Clear Longword |
None.
The scalar src or vector operand Va is combined, elementwise, using the specified Boolean function, with vector register Vb and the result is written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of Vb are written into bits <63:32> of the corresponding elements of Vc. The length of the vector is specified by the Vector Length Register (VLR).
Vector Shift Logical
vector shift count:Architecture
{VVSRLL|VVSLLL [/V[0|1]] Va, Vb, Vcscalar shift count:
{VSSRLL|VSSLLL [/V[0|1]] cnt, Vb, Vc
vector shift count: opcode cntrl.rw
scalar shift count: opcode cntrl.rw, cnt.rl
| E0FD | VVSRLL | Vector Vector Shift Right Logical Longword |
| E4FD | VVSLLL | Vector Vector Shift Left Logical Longword |
| E1FD | VSSRLL | Vector Scalar Shift Right Logical Longword |
| E5FD | VSSLLL | Vector Scalar Shift Left Logical Longword |
None.
Each element in vector register Vb is shifted logically left or right 0 to 31 bits as specified by a scalar count operand or vector register Va. The shifted results are written to vector register Vc. Zero bits are propagated into the vacated bit positions. Only bits <4:0> of the count operand and bits <31:0> of each Vb element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).
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