Document revision date: 30 March 2001
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OpenVMS MACRO-32 Porting and User's Guide


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D
Data
    embedded in code #1
    embedded in code #2
    overwriting
    See also Aligning data
/DEBUG qualifier
    ALL option
    NONE option
    SYMBOLS option
    TRACEBACK option
Debugging compiled code
    $ARGn symbols
    differences from debugging assembled code
    symbols for routine arguments
    treatment of routine arguments
    with floating-point data
    with packed decimal data
.DEFAULT directive
.DEFINE_PAL directive
Descriptor formats
    checking with $IS_DESC macro
Development environment
Diagnostic messages
    disabling reporting
    interpreting
/DIAGNOSTICS qualifier
Differences between compiler and assembler
    instruction scheduling #1
    instruction scheduling #2
    interleaved instructions #1
    interleaved instructions #2
    reserved operand faults
Directives #1
Directives #2
    unsupported #1
    unsupported #2
.DISABLE ABSOLUTE directive
.DISABLE directive
    FLAGGING option
    OVERFLOW option
    QUADWORD option #1
    QUADWORD option #2
/DISABLE qualifier
    FLAGGING option #1
    FLAGGING option #2
    OVERFLOW option #1
    OVERFLOW option #2
    QUADWORD option #1
    QUADWORD option #2
.DISABLE TRUNCATION directive
DRAINA instruction
Dynamic image relocation
E
emphasis>(Alpha Architecture Reference Manual)
Emulation library
    required files
.ENABLE ABSOLUTE directive
.ENABLE directive
    FLAGGING option
    OVERFLOW option
    QUADWORD option #1
    QUADWORD option #2
/ENABLE qualifier
    FLAGGING option
    OVERFLOW option
    QUADWORD option #1
    QUADWORD option #2
.ENABLE TRUNCATION directive
Entry-point directives #1
Entry-point directives #2
Entry-point directives #3
Entry-point directives #4
Entry-point directives #5
Entry-point directives #6
    register sets
    when to use
Entry-point register arguments
    compiler hints
    declaring
    input
Entry-point register set
    declaring
    scratch
Entry points
    when to declare
Epilogue code
    preserving registers #1
    preserving registers #2
    using REI to change modes
Error messages
    interpreting
ESCD instruction
ESCE instruction
ESCF instruction
EV6 Alpha processor #1
EV6 Alpha processor #2
EVAX_CALLG_64 built-in
    64-bit address support #1
    64-bit address support #2
EVAX_SEXTL built-in
    sign extension for 64-bit address support #1
    sign extension for 64-bit address support #2
.EVEN directive
Event flags
    synchronization guarantees
Exception entry point
    declaring #1
    declaring #2
Exception handlers
    modifying
.EXCEPTION_ENTRY directive #1
.EXCEPTION_ENTRY directive #2
.EXCEPTION_ENTRY directive #3
.EXCEPTION_ENTRY directive #4
EXE$REI_INIT_STACK
    using to change mode
F
Faults
    reserved operand
/FLAG qualifier #1
/FLAG qualifier #2
/FLAG qualifier #3
/FLAG qualifier #4
Flagging
    disabling #1
    disabling #2
    disabling #3
    enabling #1
    enabling #2
    specifying
Floating-point data
    debugging code with
Floating-point instructions
Flow control mechanisms
    branches from JSB routines
    condition codes
FP
    Alpha register
    modifying
    negative offsets
    positive offsets
    referencing local storage
Frame pointer (FP)
    See FP
G
Generated code #1
Generated code #2
    detecting
.GLOBAL_LABEL directive
Granularity
    byte and word-write operations #1
    byte and word-write operations #2
    byte and word-write operations #3
    interlocked instructions
Granularity controls
    subordinate to atomicity
H
Hints
    enabling #1
    enabling #2
    for specifying registers #1
    for specifying registers #2
Homed argument list
    $ARGn symbols
    detecting
home_arg argument
    .CALL_ENTRY directive
I
Image
    relocating
Informational messages
    disabling reporting
Input register argument
Input register mask
Input register set #1
Input register set #2
Input register set #3
Instruction scheduling
    differences between VAX and Alpha
    optimization
Instruction size
    dependency on
Instruction stream
    data embedded in #1
    data embedded in #2
    modifying
Instructions
    Alpha #1
    Alpha #2
    Alpha #3
    compiler built-ins for Alpha assembly language
    floating-point
    incomplete
    interleaving
    interlocked memory
    packed decimal
    unsupported
    using Alpha #1
    using Alpha #2
    using Alpha #3
Interlocked instructions
    atomicity
    synchronization guarantees
Interlocked queue instructions
    synchronization guarantees
Internal processor registers
    See IPRs
IPRs (internal processor registers)
$IS_32BITS macro
    checking sign extension #1
    checking sign extension #2
    checking sign extension #3
$IS_DESC macro
    checking if format descriptor is 64-bit
$IS_DESC64 macro
    checking if format descriptor is 64-bit


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