Document revision date: 19 July 1999
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VAX MACRO and Instruction Set Reference Manual


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ACB

Add Compare and Branch

Format

opcode limit.rx, add.rx, index.mx, displ.bw

Condition Codes

N|| <--- index LSS 0;  
Z|| <--- index EQL 0;  
V|| <--- {integer overflow};  
C|| <--- C;  

Exceptions

Opcodes

9D ACBB Add Compare and Branch Byte
3D ACBW Add Compare and Branch Word
F1 ACBL Add Compare and Branch Long
4F ACBF Add Compare and Branch F_floating
4FFD ACBG Add Compare and Branch G_floating
6F ACBD Add Compare and Branch D_floating
6FFD ACBH Add Compare and Branch H_floating

Description

The addend operand is added to the index operand and the index operand is replaced by the result. The index operand is compared with the limit operand. If the addend operand is positive (or zero) and the comparison is less than or equal to zero, or if the addend is negative and the comparison is greater than or equal to zero, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

  1. ACB efficiently implements the general FOR or DO loops in high-level languages, since the sense of the comparison between index and limit is dependent on the sign of the addend.
  2. On integer overflow, the index operand is replaced by the low-order bits of the true result. Comparison and branch determination proceed normally on the updated index operand.
  3. On floating underflow, if FU is clear, the index operand is replaced by zero, and comparison and branch determination proceed normally. A fault occurs if FU is set, and the index operand is unaffected.
  4. On floating overflow, the instruction takes a floating overflow fault, and the index operand is unaffected.
  5. On a reserved operand fault, the index operand is unaffected, and condition codes are UNPREDICTABLE.
  6. Except for the circumstance described in note 5, the C-bit is unaffected.

AOBLEQ

Add One and Branch Less Than or Equal

Format

opcode limit.rl, index.ml, displ.bb

Condition Codes

N|| <--- index LSS 0;  
Z|| <--- index EQL 0;  
V|| <--- {integer overflow};  
C|| <--- C;  

Exceptions

Opcodes

F3 AOBLEQ Add One and Branch Less Than or Equal

Description

One is added to the index operand, and the index operand is replaced by the result. The index operand is compared with the limit operand. If the comparison is less than or equal to zero, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

  1. Integer overflow occurs if the index operand before addition is the largest positive integer. On overflow, the index operand is replaced by the largest negative integer, and the branch is taken.
  2. The C-bit is unaffected.

AOBLSS

Add One and Branch Less Than

Format

opcode limit.rl, index.ml, displ.bb

Condition Codes

N|| <--- index LSS 0;  
Z|| <--- index EQL 0;  
V|| <--- {integer overflow};  
C|| <--- C;  

Exceptions

Opcodes

F2 AOBLSS Add One and Branch Less Than

Description

One is added to the index operand and the index operand is replaced by the result. The index operand is compared with the limit operand. If the comparison result is less than zero, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

  1. Integer overflow occurs if the index operand before addition is the largest positive integer. On overflow, the index operand is replaced by the largest negative integer, and thus (unless the limit operand is the largest negative integer), the branch is taken.
  2. The C-bit is unaffected.

B

Branch on (condition)

Format

opcode displ.bb

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes
14 {N OR Z} EQL 0 BGTR Branch on Greater Than (signed)
15 {N OR Z} EQL 1 BLEQ Branch on Less Than or Equal (signed)
12 Z EQL 0 BNEQ, Branch on Not Equal (signed)
    BNEQU Branch on Not Equal Unsigned
13 Z EQL 1 BEQL, Branch on Equal (signed)
    BEQLU Branch on Equal Unsigned
18 N EQL 0 BGEQ Branch on Greater Than or Equal (signed)
19 N EQL 1 BLSS Branch on Less Than (signed)
1A {C OR Z} EQL 0 BGTRU Branch on Greater Than Unsigned
1B {C OR Z} EQL 1 BLEQU Branch Less Than or Equal Unsigned
1C V EQL 0 BVC Branch on Overflow Clear
1D V EQL 1 BVS Branch on Overflow Set
1E C EQL 0 BGEQU, Branch on Greater Than or Equal Unsigned
    BCC Branch on Carry Clear
1F C EQL 1 BLSSU, Branch on Less Than Unsigned
    BCS Branch on Carry Set

Description

The condition codes are tested. If the condition indicated by the instruction is met, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

The VAX conditional branch instructions permit considerable flexibility in branching but require care in choosing the correct branch instruction. The conditional branch instructions are best seen as three overlapping groups:

  1. Overflow and Carry Group
    BVS V EQL 1
    BVC V EQL 0
    BCS C EQL 1
    BCC C EQL 0

    Typically, you would use these instructions to check for overflow (when overflow traps are not enabled), for multiprecision arithmetic, and for other special purposes.
  2. Unsigned Group
    BLSSU C EQL 1
    BLEQU {C OR Z} EQL 1
    BEQLU Z EQL 1
    BNEQU Z EQL 0
    BGEQU C EQL 0
    BGTRU {C OR Z} EQL 0

    These instructions typically follow integer and field instructions where the operands are treated as unsigned integers, address instructions, and character string instructions.
  3. Signed Group
    BLSS N EQL 1
    BLEQ {N OR Z} EQL 1
    BEQL Z EQL 1
    BNEQ Z EQL 0
    BGEQ N EQL 0
    BGTR {N OR Z} EQL 0

    These instructions typically follow floating-point instructions, decimal string instructions, and integer and field instructions where the operands are being treated as signed integers.

BB

Branch on Bit

Format

opcode pos.rl, base.vb, displ.bb

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes

E0 BBS Branch on Bit Set
E1 BBC Branch on Bit Clear

Description

The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

  1. A reserved operand fault occurs if pos GTRU 31 and the bit specified is contained in a register.
  2. On a reserved operand fault, the condition codes are UNPREDICTABLE.

BB

Branch on Bit (and modify without interlock)

Format

opcode pos.rl, base.vb, displ.bb

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes

E2 BBSS Branch on Bit Set and Set
E3 BBCS Branch on Bit Clear and Set
E4 BBSC Branch on Bit Set and Clear
E5 BBCC Branch on Bit Clear and Clear

Description

The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result. Regardless of whether the branch is taken or not, the tested bit is put in the new state as indicated by the instruction.

Notes

  1. A reserved operand fault occurs if pos GTRU 31 and the bit is contained in a register.
  2. On a reserved operand fault, the field is unaffected, and the condition codes are UNPREDICTABLE.
  3. The modification of the bit is not an interlocked operation. See BBSSI and BBCCI for interlocking instructions.

BB

Branch on Bit Interlocked

Format

opcode pos.rl, base.vb, displ.bb

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes

E6 BBSSI Branch on Bit Set and Set Interlocked
E7 BBCCI Branch on Bit Clear and Clear Interlocked

Description

The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result. Regardless of whether the branch is taken, the tested bit is put in the new state as indicated by the instruction. If the bit is contained in memory, the reading of the state of the bit and the setting of the bit to the new state is an interlocked operation. No other processor or I/O device can do an interlocked access on this bit during the interlocked operation.

Notes

  1. A reserved operand fault occurs if pos GTRU 31 and the specified bit is contained in a register.
  2. On a reserved operand fault, the field is unaffected, and the condition codes are UNPREDICTABLE.
  3. Except for memory interlocking, BBSSI is equivalent to BBSS, and BBCCI is equivalent to BBCC.
  4. This instruction is designed to modify interlocks with other processors or devices. For example, to implement "busy waiting":


    1$:    BBSSI   bit,base,1$ 
    


BLB

Branch on Low Bit

Format

opcode src.rl, displ.bb

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes

E8 BLBS Branch on Low Bit Set
E9 BLBC Branch on Low Bit Clear

Description

The low bit (bit 0) of the source operand is tested. If it is equal to the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

BR

Branch

Format

opcode displ.bx

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes

11 BRB Branch with Byte Displacement
31 BRW Branch with Word Displacement

Description

The sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

BSB

Branch to Subroutine

Format

opcode displ.bx

Condition Codes

N|| <--- N;  
Z|| <--- Z;  
V|| <--- V;  
C|| <--- C;  

Exceptions

Opcodes

10 BSBB Branch to Subroutine with Byte Displacement
30 BSBW Branch to Subroutine with Word Displacement

Description

The program counter (PC) is pushed on the stack as a longword. The sign-extended branch displacement is added to the PC, and the PC is replaced by the result.


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