Updated: 11 December 1998

VAX MACRO and Instruction Set Reference Manual

Add Compare and Branch

Format

opcode limit.rx, add.rx, index.mx, displ.bw

Condition Codes

Exceptions

• integer overflow
• floating overflow
• floating underflow
• reserved operand

Opcodes

Description

The addend operand is added to the index operand and the index operand is replaced by the result. The index operand is compared with the limit operand. If the addend operand is positive (or zero) and the comparison is less than or equal to zero, or if the addend is negative and the comparison is greater than or equal to zero, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

1. ACB efficiently implements the general FOR or DO loops in high-level languages, since the sense of the comparison between index and limit is dependent on the sign of the addend.
2. On integer overflow, the index operand is replaced by the low-order bits of the true result. Comparison and branch determination proceed normally on the updated index operand.
3. On floating underflow, if FU is clear, the index operand is replaced by zero, and comparison and branch determination proceed normally. A fault occurs if FU is set, and the index operand is unaffected.
4. On floating overflow, the instruction takes a floating overflow fault, and the index operand is unaffected.
5. On a reserved operand fault, the index operand is unaffected, and condition codes are UNPREDICTABLE.
6. Except for the circumstance described in note 5, the C-bit is unaffected.

Add One and Branch Less Than or Equal

Format

opcode limit.rl, index.ml, displ.bb

Condition Codes

Exceptions

• integer overflow

Opcodes

Description

One is added to the index operand, and the index operand is replaced by the result. The index operand is compared with the limit operand. If the comparison is less than or equal to zero, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

1. Integer overflow occurs if the index operand before addition is the largest positive integer. On overflow, the index operand is replaced by the largest negative integer, and the branch is taken.
2. The C-bit is unaffected.

Add One and Branch Less Than

Format

opcode limit.rl, index.ml, displ.bb

Condition Codes

Exceptions

• integer overflow

Opcodes

Description

One is added to the index operand and the index operand is replaced by the result. The index operand is compared with the limit operand. If the comparison result is less than zero, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

1. Integer overflow occurs if the index operand before addition is the largest positive integer. On overflow, the index operand is replaced by the largest negative integer, and thus (unless the limit operand is the largest negative integer), the branch is taken.
2. The C-bit is unaffected.

Branch on (condition)

Format

opcode displ.bb

Condition Codes

Exceptions

• None.

Description

The condition codes are tested. If the condition indicated by the instruction is met, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

The VAX conditional branch instructions permit considerable flexibility in branching but require care in choosing the correct branch instruction. The conditional branch instructions are best seen as three overlapping groups:

1. Overflow and Carry Group

   BVS	V EQL 1
   BVC	V EQL 0
   BCS	C EQL 1
   BCC	C EQL 0

   
   Typically, you would use these instructions to check for overflow (when overflow traps are not enabled), for multiprecision arithmetic, and for other special purposes.
2. Unsigned Group

   BLSSU	C EQL 1
   BLEQU	{C OR Z} EQL 1
   BEQLU	Z EQL 1
   BNEQU	Z EQL 0
   BGEQU	C EQL 0
   BGTRU	{C OR Z} EQL 0

   
   These instructions typically follow integer and field instructions where the operands are treated as unsigned integers, address instructions, and character string instructions.
3. Signed Group

   BLSS	N EQL 1
   BLEQ	{N OR Z} EQL 1
   BEQL	Z EQL 1
   BNEQ	Z EQL 0
   BGEQ	N EQL 0
   BGTR	{N OR Z} EQL 0

   
   These instructions typically follow floating-point instructions, decimal string instructions, and integer and field instructions where the operands are being treated as signed integers.

Branch on Bit

Format

opcode pos.rl, base.vb, displ.bb

Condition Codes

Exceptions

• reserved operand

Opcodes

Description

The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Notes

1. A reserved operand fault occurs if pos GTRU 31 and the bit specified is contained in a register.
2. On a reserved operand fault, the condition codes are UNPREDICTABLE.

Branch on Bit (and modify without interlock)

Format

opcode pos.rl, base.vb, displ.bb

Condition Codes

Exceptions

• reserved operand

Opcodes

Description

The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result. Regardless of whether the branch is taken or not, the tested bit is put in the new state as indicated by the instruction.

Notes

1. A reserved operand fault occurs if pos GTRU 31 and the bit is contained in a register.
2. On a reserved operand fault, the field is unaffected, and the condition codes are UNPREDICTABLE.
3. The modification of the bit is not an interlocked operation. See BBSSI and BBCCI for interlocking instructions.

Branch on Bit Interlocked

Format

opcode pos.rl, base.vb, displ.bb

Condition Codes

Exceptions

• reserved operand

Opcodes

Description

The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result. Regardless of whether the branch is taken, the tested bit is put in the new state as indicated by the instruction. If the bit is contained in memory, the reading of the state of the bit and the setting of the bit to the new state is an interlocked operation. No other processor or I/O device can do an interlocked access on this bit during the interlocked operation.

Notes

1. A reserved operand fault occurs if pos GTRU 31 and the specified bit is contained in a register.
2. On a reserved operand fault, the field is unaffected, and the condition codes are UNPREDICTABLE.
3. Except for memory interlocking, BBSSI is equivalent to BBSS, and BBCCI is equivalent to BBCC.
4. This instruction is designed to modify interlocks with other processors or devices. For example, to implement "busy waiting":

   1$: BBSSI bit,base,1$

Branch on Low Bit

Format

opcode src.rl, displ.bb

Condition Codes

Exceptions

• None.

Opcodes

Description

The low bit (bit 0) of the source operand is tested. If it is equal to the test state indicated by the instruction, the sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Branch

Format

opcode displ.bx

Condition Codes

Exceptions

• None.

Opcodes

Description

The sign-extended branch displacement is added to the program counter (PC), and the PC is replaced by the result.

Branch to Subroutine

Format

opcode displ.bx

Condition Codes

Exceptions

• None.

Opcodes

Description

The program counter (PC) is pushed on the stack as a longword. The sign-extended branch displacement is added to the PC, and the PC is replaced by the result.

Case

Format

opcode selector.rx, base.rx, limit.rx,

displ[0].bw,
...,
displ[limit].bw

Condition Codes

Exceptions

• None.

Opcodes

Description

The base operand is subtracted from the selector operand, and the result replaces a temporary operand. The temporary operand is compared with the limit operand; if it is less than or equal unsigned, a branch displacement selected by the temporary value is added to the program counter (PC), and the PC is replaced by the result. Otherwise, twice the sum of the limit operand and 1 is added to the PC, and the PC is replaced by the result. This operation causes the PC to be moved past the array of branch displacements. Regardless of the branch taken, the condition codes are modified as a result of the comparison of the temporary operand with the limit operand.

Notes

1. After operand evaluation, the PC points at displ[0], not to the next instruction. The branch displacements are relative to the address of displ[0].
2. The selector and base operands can both be considered as either signed or unsigned integers.

In the following example, the CASEB instruction selects one of eight displacements immediately following the instruction. The example is for illustration only. An actual instruction would use run-time variables instead of the assembly-time static values shown. Also, in an actual instruction, the displacements selected by the CASEB instruction would be branches to various routines.

.PSECT CODE, PIC, SHR, WRT, EXE, LONG TABIND: .WORD 4 .ENTRY START,^M<> CLRW R4 CLRW R5 MOVW #0,R4 MOVW #7,R5 CASEB TABIND,R4,R5 TAB: .WORD 1$-TAB .WORD 2$-TAB .WORD 3$-TAB .WORD 4$-TAB .WORD 5$-TAB .WORD 6$-TAB .WORD 7$-TAB BRB 9$ 1$: .ASCII /AT 1/ 2$: .ASCII /AT 2/ 3$: .ASCII /AT 3/ 4$: .ASCII /AT 4/ 5$: .ASCII /AT 5/ 6$: .ASCII /AT 6/ 7$: .ASCII /AT 7/ 8$: .ASCII /AT 8/ 9$: $EXIT_S .END START

The objective of the CASE instruction is to transfer control to one of many possible locations depending on the value of "selector," or TABIND, as shown in the example. These locations are labeled in the example from 1$: to 8$:.

In the example, the table contains eight branch displacements. In all cases, the limit operand (here shown as R5, which contains a 7) is one less than the number of displacements (8) in the table. The base operand (here shown as R4, which contains a zero) is the lowest permissible value for TABIND.

The CASE instruction subtracts base (contents of R4, a zero) from the value of TABIND to produce a zero-origin index into the table. The limit (contents of R5, a 7) is compared with this index to ensure that the table limit is not exceeded.

After operand evaluation, the program counter (PC) points to TAB:. The locations to which branching occurs are represented in the table as displacements. The displacement in the table selected by TABIND is added to the PC to form a destination address. The destination selected in the example is at location 5$:. In practical usage, this location would contain a branch to a specific routine.

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