Document revision date: 19 July 1999 | |
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Test
opcode src.rx
N|| <--- src LSS 0; | |
Z|| <--- src EQL 0; | |
V|| <--- 0; | |
C|| <--- 0; |
95 | TSTB | Test Byte |
B5 | TSTW | Test Word |
D5 | TSTL | Test Long |
The condition codes are modified according to the value of the source operand.
The operand src is equivalent to CMPx src, S^#0, but is 1 byte shorter.
Exclusive OR
2operand: opcode mask.rx, dst.mx
3operand: opcode mask.rx, src.rx, dst.wx
N|| <--- dst LSS 0; | |
Z|| <--- dst EQL 0; | |
V|| <--- 0; | |
C|| <--- C; |
8C | XORB2 | Exclusive OR Byte 2 Operand |
8D | XORB3 | Exclusive OR Byte 3 Operand |
AC | XORW2 | Exclusive OR Word 2 Operand |
AD | XORW3 | Exclusive OR Word 3 Operand |
CC | XORL2 | Exclusive OR Long 2 Operand |
CD | XORL3 | Exclusive OR Long 3 Operand |
In 2 operand format, the result of the logical XOR on the mask operand and the destination operand replaces the destination operand. In 3 operand format, the result of the logical XOR on the mask operand and the source operand replaces the destination operand.
9.2.2 Address Instructions
The following instructions are described in this section.
Description and Opcode | Number of Instructions | |
---|---|---|
1. |
Move Address
MOVA{B,W,L=F,Q=D=G,O=H} src.ax, dst.wl |
5 |
2. |
Push Address
PUSHA{B,W,L=F,Q=D=G,O=H} src.ax, {-(SP).wl} |
5 |
Move Address
opcode src.ax, dst.wl
N|| <--- dst LSS 0; | |
Z|| <--- dst EQL 0; | |
V|| <--- 0; | |
C|| <--- C; |
9E | MOVAB | Move Address Byte |
3E | MOVAW | Move Address Word |
DE | MOVAL | Move Address Long |
MOVAF | Move Address F_floating | |
7E | MOVAQ | Move Address Quad |
MOVAD | Move Address D_floating | |
MOVAG | Move Address G_floating | |
7EFD | MOVAH | Move Address H_floating |
MOVAO | Move Address Octa |
The destination operand is replaced by the source operand. The context in which the source operand is evaluated is given by the data type of the instruction. The operand whose address replaces the destination operand is not referenced.
The access type of the source operand is address, which causes the address of the specified operand to be moved.
Push Address
opcode src.ax
N|| <--- src LSS 0; | |
Z|| <--- src EQL 0; | |
V|| <--- 0; | |
C|| <--- C; |
9F | PUSHAB | Push Address Byte |
3F | PUSHAW | Push Address Word |
DF | PUSHAL | Push Address Long, |
PUSHAF | Push Address F_floating | |
7F | PUSHAQ | Push Address Quad, |
PUSHAD | Push Address D_floating, | |
PUSHAG | Push Address G_floating | |
7FFD | PUSHAH | Push Address H_floating |
PUSHAO | Push Address Octa |
The source operand is pushed on the stack. The context in which the source operand is evaluated is given by the data type of the instruction. The operand whose address is pushed is not referenced.
9.2.3 Variable-Length Bit Field Instructions
A variable-length bit field is specified by the following three
operands:
Zero bytes are referenced if the field size is zero.
The following instructions are described in this section.
Description and Opcode | Number of Instructions | |
---|---|---|
1. |
Compare Field
CMPV pos.rl, size.rb, base.vb, {field.rv}, src.rl |
1 |
2. |
Compare Zero-Extended Field
CMPZV pos.rl, size.rb, base.vb, {field.rv}, src.rl |
1 |
3. |
Extract Field
EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wl |
1 |
4. |
Extract Zero-Extended Field
EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl |
1 |
5. |
Find First
FF{S,C} startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl |
2 |
6. |
Insert Field
INSV src.rl, pos.rl, size.rb, base.vb, {field.wv} |
1 |
The following variable-length bit field instructions are described in Section 9.2.4:
Description and Opcode | Number of Instructions | |
---|---|---|
1. |
Branch on Bit
BB{S,C} pos.rl, base.vb, displ.bb, {field.rv} |
2 |
2. |
Branch on Bit (and modify without interlock)
BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv} |
4 |
3. |
Branch on Bit (and modify) Interlocked
BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv} |
2 |
Compare Field
opcode pos.rl, size.rb, base.vb, src.rl
N|| <--- tmp LSS src; | |
Z|| <--- tmp EQL src; | |
V|| <--- 0; | |
C|| <--- tmp LSSU src; |
EC | CMPV | Compare Field |
ED | CMPZV | Compare Zero-Extended Field |
The field specified by the position, size, and base operands is compared with the source operand. For CMPV, the source operand is compared with the sign-extended field. For CMPZV, the source operand is compared with the zero-extended field. The only action is to affect the condition codes.
Extract Field
opcode pos.rl, size.rb, base.vb, dst.wl
N|| <--- dst LSS 0; | |
Z|| <--- dst EQL 0; | |
V|| <--- 0; | |
C|| <--- C; |
EE | EXTV | Extract Field |
EF | EXTZV | Extract Zero-Extended Field |
For EXTV, the destination operand is replaced by the sign-extended field specified by the position, size, and base operands. For EXTZV, the destination operand is replaced by the zero-extended field specified by the position, size, and base operands. If the size operand is zero, the only action is to replace the destination operand with zero and to modify the condition codes.
Find First
opcode startpos.rl, size.rb, base.vb, findpos.wl
N|| <--- 0; | |
Z|| <--- {bit not found}; | |
V|| <--- 0; | |
C|| <--- 0; |
EB | FFC | Find First Clear |
EA | FFS | Find First Set |
A field specified by the start position, size, and base operands is extracted. Starting at bit 0 and extending to the highest bit in the field, the field is tested for a bit in the state indicated by the instruction. If a bit in the indicated state is found, the find position operand is replaced by the position of the bit, and the Z condition code bit is cleared. If no bit in the indicated state is found, the find position operand is replaced by the position (relative to the base) of a bit one position to the left of the specified field, and the Z condition code bit is set. If the size operand is zero, the find position operand is replaced by the start position operand, and the Z condition code bit is set.
Insert Field
opcode src.rl, pos.rl, size.rb, base.vb
N|| <--- N; | |
Z|| <--- Z; | |
V|| <--- V; | |
C|| <--- C; |
F0 | INSV | Insert Field |
The field specified by the position, size, and base operands is replaced by bits size-1:0 of the source operand. If the size operand is zero, the instruction has no effect.
9.2.4 Control Instructions
In most implementations of the VAX architecture, improved execution
speed will result if the target of a control instruction is on an
aligned longword boundary.
The following instructions are described in this section.
Description and Opcode | Number of Instructions | |||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1. |
Add Compare and Branch
ACB{B,W,L,F,D,G,H} limit.rx, add.rx, index.mx, displ.bw Compare is LE on positive add, GE on negative add. |
7 | ||||||||||||||||||||||||||
2. |
Add One and Branch Less Than or Equal
AOBLEQ limit.rl, index.ml, displ.bb |
1 | ||||||||||||||||||||||||||
3. |
Add One and Branch Less Than
AOBLSS limit.rl, index.ml, displ.bb |
1 | ||||||||||||||||||||||||||
4. |
Conditional Branch
|
12 | ||||||||||||||||||||||||||
5. |
Branch on Bit
BB{S,C} pos.rl, base.vb, displ.bb, {field.rv} |
2 | ||||||||||||||||||||||||||
6. |
Branch on Bit
(and modify without interlock) BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv} |
4 | ||||||||||||||||||||||||||
7. |
Branch on Bit (and modify) Interlocked
BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv} |
2 | ||||||||||||||||||||||||||
8. |
Branch on Low Bit
BLB{S,C} src.rl, displ.bb |
2 | ||||||||||||||||||||||||||
9. |
Branch with {Byte, Word} Displacement
BR{B,W} displ.bx |
2 | ||||||||||||||||||||||||||
10. |
Branch to Subroutine with {Byte, Word}
Displacement BSB{B,W} displ.bx, {--(SP).wl} |
2 | ||||||||||||||||||||||||||
11. |
Case
CASE{B,W,L} selector.rx, base.rx, limit.rx, displ.bw-list |
3 | ||||||||||||||||||||||||||
12. |
Jump
JMP dst.ab |
1 | ||||||||||||||||||||||||||
13. |
Jump to Subroutine
JSB dst.ab, {--(SP).wl} |
1 | ||||||||||||||||||||||||||
14. |
Return from Subroutine
RSB {(SP)+.rl} |
1 | ||||||||||||||||||||||||||
15. |
Subtract One and Branch Greater Than
or Equal SOBGEQ index.ml, displ.bb |
1 | ||||||||||||||||||||||||||
16. |
Subtract One and Branch Greater Than
SOBGTR index.ml, displ.bb |
1 |
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