Document revision date: 30 March 2001

Test

Format

opcode src.rx

Condition Codes

Exceptions

None.

Opcodes

Description

The condition codes are modified according to the value of the source operand.

Note

The operand src is equivalent to CMPx src, S^#0, but is 1 byte shorter.

Exclusive OR

Format

2operand: opcode mask.rx, dst.mx

3operand: opcode mask.rx, src.rx, dst.wx

Condition Codes

Exceptions

None.

Opcodes

Description

In 2 operand format, the result of the logical XOR on the mask operand and the destination operand replaces the destination operand. In 3 operand format, the result of the logical XOR on the mask operand and the source operand replaces the destination operand.

9.2.2 Address Instructions

Move Address

Format

opcode src.ax, dst.wl

Condition Codes

Exceptions

None.

Opcodes

Description

The destination operand is replaced by the source operand. The context in which the source operand is evaluated is given by the data type of the instruction. The operand whose address replaces the destination operand is not referenced.

Note

The access type of the source operand is address, which causes the address of the specified operand to be moved.

Push Address

Format

opcode src.ax

Condition Codes

Exceptions

None.

Opcodes

Description

The source operand is pushed on the stack. The context in which the source operand is evaluated is given by the data type of the instruction. The operand whose address is pushed is not referenced.

Notes

1. PUSHAx src is equivalent to MOVAx src, -(SP), but is one byte shorter.
2. The source operand is of address access type, which causes the address of the specified operand to be pushed.

9.2.3 Variable-Length Bit Field Instructions

1. A longword position operand.
2. A byte field size operand in the range 0 to 32; if out of this range, a reserved operand fault occurs.
3. A base address. Use the position operand to locate the bit field relative to this base address. The address is obtained from an operand of address access type. However, unlike other instances of operand specifiers of address access type, register mode can be designated in the operand specifier. In this case, the field is contained in the register n designated by the operand specifier (or register n+1 concatenated with register n). (See Chapter 8.) If the field is contained in a register and the size operand is not zero, the position operand must have a value in the range 0 to 31, or a reserved operand fault occurs.

Zero bytes are referenced if the field size is zero.

The following instructions are described in this section.

	Description and Opcode	Number of Instructions
1.	Compare Field CMPV pos.rl, size.rb, base.vb, {field.rv}, src.rl	1
2.	Compare Zero-Extended Field CMPZV pos.rl, size.rb, base.vb, {field.rv}, src.rl	1
3.	Extract Field EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wl	1
4.	Extract Zero-Extended Field EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl	1
5.	Find First FF{S,C} startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl	2
6.	Insert Field INSV src.rl, pos.rl, size.rb, base.vb, {field.wv}	1

The following variable-length bit field instructions are described in Section 9.2.4:

	Description and Opcode	Number of Instructions
1.	Branch on Bit BB{S,C} pos.rl, base.vb, displ.bb, {field.rv}	2
2.	Branch on Bit (and modify without interlock) BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv}	4
3.	Branch on Bit (and modify) Interlocked BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv}	2

Compare Field

Format

opcode pos.rl, size.rb, base.vb, src.rl

Condition Codes

Exceptions

reserved operand

Opcodes

Description

The field specified by the position, size, and base operands is compared with the source operand. For CMPV, the source operand is compared with the sign-extended field. For CMPZV, the source operand is compared with the zero-extended field. The only action is to affect the condition codes.

Notes

1. A reserved operand fault occurs if:
   • size GTRU 32
   • pos GTRU 31, size NEQ 0, and the field is contained in the registers
2. On a reserved operand fault, the condition codes are UNPREDICTABLE.

Extract Field

Format

opcode pos.rl, size.rb, base.vb, dst.wl

Condition Codes

Exceptions

reserved operand

Opcodes

Description

For EXTV, the destination operand is replaced by the sign-extended field specified by the position, size, and base operands. For EXTZV, the destination operand is replaced by the zero-extended field specified by the position, size, and base operands. If the size operand is zero, the only action is to replace the destination operand with zero and to modify the condition codes.

Notes

1. A reserved operand fault occurs if:
   • size GTRU 32
   • pos GTRU 31, size NEQ 0, and the field is contained in the registers
2. On a reserved operand fault, the destination operand is unaffected, and the condition codes are UNPREDICTABLE.

Find First

Format

opcode startpos.rl, size.rb, base.vb, findpos.wl

Condition Codes

Exceptions

reserved operand

Opcodes

Description

A field specified by the start position, size, and base operands is extracted. Starting at bit 0 and extending to the highest bit in the field, the field is tested for a bit in the state indicated by the instruction. If a bit in the indicated state is found, the find position operand is replaced by the position of the bit, and the Z condition code bit is cleared. If no bit in the indicated state is found, the find position operand is replaced by the position (relative to the base) of a bit one position to the left of the specified field, and the Z condition code bit is set. If the size operand is zero, the find position operand is replaced by the start position operand, and the Z condition code bit is set.

Notes

1. A reserved operand fault occurs if:
   • size GTRU 32
   • startpos GTRU 31, size NEQ 0, and the field is contained in the registers
2. On a reserved operand fault, the find position operand is unaffected, and the condition codes are UNPREDICTABLE.

Insert Field

Format

opcode src.rl, pos.rl, size.rb, base.vb

Condition Codes

Exceptions

reserved operand

Opcodes

Description

The field specified by the position, size, and base operands is replaced by bits size-1:0 of the source operand. If the size operand is zero, the instruction has no effect.

Notes

1. When executing INSV, a processor may read in the entire aligned longword or longwords that contains the field, replace the field portion of the aligned longword with the source operand, and write back the entire aligned longword. Because of this, data written to the nonfield portion of the aligned longword in memory by another processor or I/O device during the execution of INSV may be written over when the INSV is completed.
2. A reserved operand fault occurs if:
   • size GTRU 32
   • pos GTRU 31, size NEQ 0, and the field is contained in the registers
3. On a reserved operand fault, the field is unaffected, and the condition codes are UNPREDICTABLE.

9.2.4 Control Instructions

The following instructions are described in this section.

	Description and Opcode	Number of Instructions
1.	Add Compare and Branch ACB{B,W,L,F,D,G,H} limit.rx, add.rx, index.mx, displ.bw Compare is LE on positive add, GE on negative add.	7
2.	Add One and Branch Less Than or Equal AOBLEQ limit.rl, index.ml, displ.bb	1
3.	Add One and Branch Less Than AOBLSS limit.rl, index.ml, displ.bb	1
4.	Conditional Branch Condition Name LSS Less Than LEQ Less Than or Equal EQL, EQLU Equal, Equal Unsigned NEQ, NEQU Not Equal, Not Equal Unsigned GEQ Greater Than or Equal GTR Greater Than LSSU, CS Less Than Unsigned, Carry Set LEQU Less Than or Equal Unsigned GEQU, CC Greater Than or Equal Unsigned, Carry Clear GTRU Greater Than Unsigned VS Overflow Set VC Overflow Clear	12
5.	Branch on Bit BB{S,C} pos.rl, base.vb, displ.bb, {field.rv}	2
6.	Branch on Bit (and modify without interlock) BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv}	4
7.	Branch on Bit (and modify) Interlocked BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv}	2
8.	Branch on Low Bit BLB{S,C} src.rl, displ.bb	2
9.	Branch with {Byte, Word} Displacement BR{B,W} displ.bx	2
10.	Branch to Subroutine with {Byte, Word} Displacement BSB{B,W} displ.bx, {-(SP).wl}	2
11.	Case CASE{B,W,L} selector.rx, base.rx, limit.rx, displ.bw-list	3
12.	Jump JMP dst.ab	1
13.	Jump to Subroutine JSB dst.ab, {-(SP).wl}	1
14.	Return from Subroutine RSB {(SP)+.rl}	1
15.	Subtract One and Branch Greater Than or Equal SOBGEQ index.ml, displ.bb	1
16.	Subtract One and Branch Greater Than SOBGTR index.ml, displ.bb	1

	privacy and legal statement
4515PRO_018.HTML