Document revision date: 19 July 1999

The operand specifier format is as follows:

Bits 15:8 contain a second operand specifier (termed the base operand specifier) for any of the addressing modes except register, literal, or index. The specification of register, literal, or index addressing mode results in an illegal addressing mode fault (see Appendix E). If the base operand specifier requires it, a specifier extension immediately follows. The base operand specifier is subject to the same restrictions as would apply if it were used alone. If the use of some particular specifier is illegal (that is, causes a fault or UNPREDICTABLE behavior) under some circumstances, then that specifier is similarly illegal as a base operand specifier in index mode under the same circumstances.

The operand to be specified by index mode addressing is termed the primary operand. You normally use the base operand specifier to determine an operand address. This address is termed the base operand address (BOA). The address of the primary operand specified is determined by multiplying the contents of the index register x by the size of the primary operand in bytes (1 for byte; 2 for word; 4 for longword and F_floating; 8 for quadword, D_floating, and G_floating; and 16 for octaword and H_floating), adding BOA, and taking the result.

OA = BOA + {size * (Rx)}
operand = (OA)

If the base operand specifier is for autoincrement or autodecrement mode, the increment or decrement size is the size in bytes of the primary operand.

Certain restrictions are placed on the index register x. You cannot use the PC as an index register. If you use it, a reserved addressing mode fault occurs (see Appendix E). If the base operand specifier is for an addressing mode that results in register modification (that is, autoincrement mode, autodecrement mode, or autoincrement deferred mode), the same register cannot be the index register. If it is, the primary operand address is UNPREDICTABLE.

The names of the addressing modes resulting from index mode addressing are formed by adding the suffix "indexed" to the addressing mode of the base operand specifier. The following list gives the names and assembler notation (the index register is designated Rx to distinguish it from the register Rn in the base operand specifier):

• Register deferred indexed--- (Rn)[Rx]
• Autoincrement indexed--- (Rn)+[Rx] or Immediate indexed--- I^#constant[Rx] (Immediate indexed is recognized by the assembler, but is not generally useful. Note that the operand address is independent of the value of the constant.)
• Autoincrement deferred indexed--- @(Rn)+[Rx] or Absolute indexed--- @#address[Rx]
• Autodecrement indexed--- --(Rn)[Rx]
• Byte, word, or longword displacement indexed--- B^D(Rn)[Rx],W^D(Rn)[Rx], or L^D(Rn)[Rx]
• Byte, word, or longword displacement deferred indexed--- @B^D(Rn)[Rx],@W^D(Rn)[Rx], or @L^D(Rn)[Rx]

This section provides summaries of general register and program counter (PC) addressing.

Table 8-5 is a summary of general register addressing and Table 8-6 is a summary of PC addressing.

8.8.1 General Register Addressing

The general register addressing format is as follows:

Table 8-5 General Register Addressing

Hex	Dec	Name	Assembler	r mw a v	PC	SP	AP FP	Can Be Indexed?
0--3	0--3	Literal	S^#literal	y f f f f	---	---	---	f
4	4	Indexed	i[Rx]	y y y y y	f	y	y	f
5	5	Register	Rn	y y y f y	u	uq	uo	f
6	6	Register deferred	(Rn)	y y y y y	u	y	y	y
7	7	Autodecrement	-(Rn)	y y y y y	u	y	y	ux
8	8	Autoincrement	(Rn)+	y y y y y	p	y	y	ux
9	9	Autoincrement	@(Rn)+	y y y y y	p	y	y	ux
		deferred
A	10	Byte displacement	B^D(Rn)	y y y y y	p	y	y	y
B	11	Byte displacement	@B^D(Rn)	y y y y y	p	y	y	y
		deferred
C	12	Word displacement	W^D(Rn)	y y y y y	p	y	y	y
D	13	Word displacement	@W^D(Rn)	y y y y y	p	y	y	y
		deferred
E	14	Longword displacement	L^D(Rn)	y y y y y	p	y	y	y
F	15	Longword displacement	@L^D(Rn)	y y y y y	p	y	y	y
		deferred

• D---Displacement
• i---Any indexable addressing mode
• -- ---Logically impossible
• f---Reserved addressing mode fault
• p---Program Counter addressing
• u---UNPREDICTABLE
• uq---UNPREDICTABLE for quadword, octaword, D _floating, H _floating, and G _floating, (and field if position and size greater than 32)
• uo---UNPREDICTABLE for octaword and H _floating
• ux---UNPREDICTABLE for index register same as base register
• y---Yes, always valid addressing mode
• r---Read access
• m---Modify access
• w---Write access
• a---Address access
• v---Field access

The program counter addressing format is as follows:

Table 8-6 Program Counter Addressing

Hex	Dec	Name	Assembler	r mw a v	Can Be Indexed?
8	8	Immediate	I^#constant	y u u y y	u
9	9	Absolute	@#address	y y y y y	y
A	10	Byte relative	B^address	y y y y y	y
B	11	Byte relative	@B^address	y y y y y	y
		deferred
C	12	Word relative	W^address	y y y y y	y
D	13	Word relative	@W^address	y y y y y	y
		deferred
E	14	Longword	L^address	y y y y y	y
		relative
F	15	Longword	@L^address	y y y y y	y
		relative deferred

• u---UNPREDICTABLE
• y---Yes, always valid addressing mode
• r---Read access
• m---Modify access
• w---Write access
• a---Address access
• v---Field access

There are two operand specifier formats.

The operand specifier is a signed byte displacement.

The operand specifier is a signed word displacement.

In branch displacement addressing, the byte or word displacement is sign extended to 32 bits and added to the updated address in the PC. The updated address in the PC is the location of the first byte beyond the operand specifier. The result is the branch address A.

A = PC + SEXT(displ)

The assembler notation for byte and word branch displacement addressing is A, where A is the branch address. Note that you must use the branch address, and not the displacement.

The following sections describe the native-mode instruction set. The instructions are divided into groups according to their function and are listed alphabetically within each group.

9.1 Introduction to the VAX Instruction Set

This section describes the instructions generally used by all software across all implementations of the VAX architecture.

You can find a more complete description of the instruction set in the VAX Architecture Reference Manual. The VAX Architecture Reference Manual also contains information on instructions that are generally used by privileged software and are specific to specialized portions of the VAX architecture, such as memory management, interrupts and exceptions, process dispatching, and processor registers.

A list of instructions and opcode assignments appears in Appendix D.

9.2 Instruction Descriptions

The instruction set is divided into the following 12 major sections:

• Integer arithmetic and logical
• Address
• Variable-length bit field
• Control
• Procedure call
• Miscellaneous
• Queue
• Floating point
• Character string
• Cyclic redundancy check (CRC)
• Decimal string
• Edit

Within each major section, instructions that are closely related are combined into groups and described together. The instruction group description is composed of the following:

• The group name.
• The format of each instruction in the group, including the name and type of each instruction operand specifier and the order in which it appears in memory. Operand specifiers from left to right appear in increasing memory addresses.
• The operation of the instruction. The operation is given as a sequence of pseudocode statements in an ALGOL-like syntax. Each VAX processor may implement the instruction in different or more efficient ways, but each processor gives results consistent with the pseudocode, English descriptions, and notes.
• The effect on condition codes.
• Exceptions specific to the instruction. Exceptions that are generally possible for all instructions (for example, illegal or reserved addressing mode, T-bit, and memory management violations) are not listed.
• The opcodes, mnemonics, and names of each instruction in the group. The opcodes are given in hexadecimal.
• A description, in English, of the instruction.
• Optional notes on the instruction and programming examples.

Operand Specifier Notation

Operand specifiers are described as follows:

name . access-type data-type

name

A mnemonic name for the operand in the context of the instruction. The name is often abbreviated.

access-type

A letter denoting the operand specifier access type:

a	Calculate the effective address of the specified operand. Address is returned in a longword that is the actual instruction operand. Context of address calculation is given by data-type; that is, size to be used in autoincrement, autodecrement, and indexing.
b	No operand reference. Operand specifier is a branch displacement. Size of branch displacement is given by data-type.
m	Operand is read, potentially modified, and written. Note that this is not an indivisible memory operation. Also note that if the operand is not actually modified, it may not be written back. However, modify type operands are always checked for both read and write accessibility.
r	Operand is read only.
v	Calculate the effective address of the specified operand. If the effective address is in memory, the address is returned in a longword that is the actual instruction operand. Context of address calculation is given by data-type. If the effective address is Rn, the operand is in Rn or R[n+1]'Rn.
w	Operand is written only.

data-type

A letter denoting the data type of the operand:

b	Byte
d	D_floating
f	F_floating
g	G_floating
h	H_floating
l	Longword
o	Octaword
q	Quadword
w	Word
x	First data type specified by instruction
y	Second data type specified by instruction

Operation Description Notation

The operation of an instruction is given as a sequence of control and assignment statements in an ALGOL-like syntax. No attempt is made to formally define the syntax; it is assumed to be familiar to the reader. The notation used is an extension of the notation introduced in Section 8.7.

+	Addition
--	Subtraction, unary minus
*	Multiplication
/	Division (quotient only)
**	Exponentiation
'	Concatenation
<-	Is replaced by
=	Is defined as
Rn or R[n]	Contents of register Rn
PC, SP, FP, or AP	The contents of register R15, R14, R13, or R12, respectively
PSW	The contents of the processor status word
PSL	The contents of the processor status longword
(x)	Contents of memory location whose address is x
(x)+	Contents of memory location whose address is x; x incremented by the size of operand referenced at x
--(x)	x decremented by size of operand to be referenced at x; contents of memory location whose address is x
<x:y>	A modifier that delimits an extent from bit position x to bit position y inclusive
<x1,x2,...,xn>	A modifier that enumerates bits x1,x2,...,xn
{ }	Arithmetic parentheses used to indicate precedence
AND	Logical AND
OR	Logical OR
XOR	Logical XOR
NOT	Logical (one's) complement
LSS	Less than signed
LSSU	Less than unsigned
LEQ	Less than or equal signed
LEQU	Less than or equal unsigned
EQL	Equal signed
EQLU	Equal unsigned
NEQ	Not equal signed
NEQU	Not equal unsigned
GEQ	Greater than or equal signed
GEQU	Greater than or equal unsigned
GTR	Greater than signed
GTRU	Greater than unsigned
SEXT(x)	x is sign extended to size of operand needed
ZEXT(x)	x is zero extended to size of operand needed
REM(x,y)	Remainder of x divided by y, such that x/y and REM(x,y) have the same sign
MINU(x,y)	Minimum unsigned of x and y
MAXU(x,y)	Maximum unsigned of x and y

Use the following conventions:

• Other than alterations caused by (x)+, or --(x), and the advancement of the program counter (PC), only operands or portions of operands appearing on the left side of assignment statements are affected.
• No operator precedence is assumed, except that replacement (<-) has the lowest precedence. Precedence is indicated explicitly by { }.
• All arithmetic, logical, and relational operators are defined in the context of their operands. For example, "+" applied to floating operands means a floating add, while "+" applied to byte operands is an integer byte add. Similarly, "LSS" is a floating comparison when applied to floating operands, while "LSS" is an integer byte comparison when applied to byte operands.
• Instruction operands are evaluated according to the operand specifier conventions (see Chapter 8). The order in which operands appear in the instruction description has no effect on the order of evaluation.
• Condition codes generally indicate the effect of an operation on the value of actual stored results, not on "true" results (which might be generated internally to greater precision). For example, two positive integers can be added together and the sum stored as a negative value because of overflow. The condition codes indicate a negative value even though the "true" result is clearly positive.

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