VAX MACRO and Instruction Set Reference Manual

Updated: 11 December 1998

VAX MACRO and Instruction Set Reference Manual

Contents

Index

IOTA

Generate Compressed Iota Vector

Format

IOTA [/0|1] stride, Vc

Architecture

Format

opcode cntrl.rw, stride.rl

Opcodes

EDFD IOTA Generate Compressed Iota Vector

vector_control_word

Exceptions

None.

Description

IOTA constructs a vector of offsets for use by the vector gather/scatter instructions VGATH and VSCAT.
IOTA first generates an iota vector of length VLR using the stride operand. An iota vector is a vector whose first element is zero and whose subsequent elements are spaced by the stride increment. The stride can be positive, negative, or zero. For example:
0*stride, 1*stride, 2*stride, 3*stride, ..., {VLR-1}*stride
The iota vector is then compressed using the contents of the Vector Mask Register (VMR). Elements of the iota vector for which the corresponding Vector Mask Register bit matches cntrl<MTF> are written in contiguous elements of the destination vector register Vc. Only bits <31:0> of each iota and destination vector element participate in the operation. Bits <63:32> of the destination vector elements are UNPREDICTABLE.
The number of elements written to Vc is returned in the Vector Count Register (VCR). The values of elements in the destination vector register between the new value of VCR and the vector length are UNPREDICTABLE.

Note
If a large value is specified for the stride.rl operand, there is a chance for integer overflow during calculation of the "tmp <- tmp + stride" step. In this case, the overflow is ignored. For example:

tmp <- tmp + stride Value of tmp before above step: FFFFFF00 Value of Stride: FFFFFF00 Value of tmp + stride: 1 FFFFFE00 Since the overflow is ignored, the new value of tmp is FFFFFE00.

10.15 Miscellaneous Instructions

This section describes VAX vector architecture miscellaneous instructions.

MFVP

Move from Vector Processor

Format

{MFVCR|MFVLR|MFVMRLO|MFVMRHI|SYNCH|MSYNCH} dst

Architecture

Format

opcode regnum.rw, dst.wl

Opcodes

31FD MFVP Move from Vector Processor

vector_control_word

None.

Exceptions

None.

MFVP instructions that specify reserved values of the regnum operand produce UNPREDICTABLE results.

Description

This instruction can be used to read the Vector Count, Length, and Mask Registers, and to synchronize a scalar processor with its associated vector processor.
When the scalar processor issues an MFVP instruction to the vector processor, the scalar processor waits for the MFVP result to be written before processing other instructions.
MFVP from VCR or VLR does not read that register until all previous write operations to the register are completed. MFVP from VMR<31:0> or VMR<63:32> does not read that longword of VMR until all previous write operations to the same longword of VMR are completed; however, this is not true for previous write operations to the other longword.
SYNC allows software to ensure that the unreported exceptions of all previously issued vector instructions (including vector memory instructions in asynchronous memory management mode) are detected and reported to the scalar processor before the scalar processor proceeds with further instructions. For more details about SYNC and its exception reporting nature refer to Section 10.7.1, Scalar/Vector Instruction Synchronization.
MSYNC allows software to ensure that all previously issued memory instructions of the scalar/vector processor pair are complete before the scalar processor proceeds with further instructions. For more details about MSYNC and its exception reporting nature, refer to Section 10.7.2, Memory Instruction Synchronization.
The value of the vector control register (VCR, VLR, VMR<31:0>, VMR<63:32>) delivered by an MFVP depends upon the value of certain vector register elements and vector control register bits. Unreported exceptions that occur in the production of these elements and control register bits are reported by the vector processor prior to the completion of the MFVP from the vector control register.
In addition, there are vector register elements and vector control register bits that the value of a vector control register delivered by an MFVP does not depend upon. It is UNPREDICTABLE whether unreported exceptions that occur in the production of these elements and control register bits are reported by the vector processor prior to the completion of the MFVP from the vector control register. Software must not rely upon the reporting of these exceptions prior to the completion of the MFVP for the correctness of program results.
Section 10.5.3.3, Dependencies Among Vector Results, gives the necessary rules to determine what vector control register elements and vector control register bits the value of a vector control register delivered by an MFVP depends upon. Examples of MFVP exception reporting using these rules are found in Section 10.6.5.
When a vector arithmetic exception or memory management exception (in asynchronous memory management mode) is reported prior to the completion of an MFVP, the following occur:

The operation of the MFVP does not complete.
No longword result is written to the scalar destination of the MFVP by the scalar processor.
The MFVP itself (rather than the next vector instruction) takes either a vector processor disabled fault or a memory management fault.

After the appropriate fault has been serviced, the MFVP may be returned to through an REI. If both exception conditions are encountered by an MFVP, then the MFVP itself takes a vector processor disabled fault. In this case, after the vector processor disabled fault has been serviced, returning to the MFVP instruction will cause the asynchronous memory management exception to be reported.

MTVP

Move to Vector Processor

Format

{MTVCR|MTVLR|MTVMRLO|MTVMRHI} src

Architecture

Format

opcode regnum.rw, src.rl

Opcodes

A9FD MTVP Move to Vector Processor

vector_control_word

None.

Exceptions

None.

Move to Vector Processor instructions that specify reserved values of the regnum operand produce UNPREDICTABLE results.

Description

This instruction can be used to write the Vector Count, Length, and Mask Registers.
The new value of VCR, VLR, or VMR does not affect any prior instructions. The new value remains in effect for all subsequent vector instructions executed until a new value is loaded.

VSYNC

Synchronize Vector Memory Access

Format

VSYNCH

Architecture

Format

opcode regnum.rw

Opcodes

A8FD VSYNC Synchronize Vector Memory Access

vector_control_word

None.

Exceptions

None.

Synchronize Vector Memory Access instructions that specify reserved values of the regnum operand produce UNPREDICTABLE results.

Description

The VSYNC instruction can be used to synchronize memory access within the vector processor. The instruction allows software to order the conflicting memory accesses of vector-memory instructions issued after VSYNC with those of vector-memory instructions issued before VSYNC. Specifically, VSYNC forces the access of a memory location by any subsequent vector-memory instruction to wait for (depend upon) the completion of all prior conflicting accesses of that location by previous vector-memory instructions. See Section 10.7.1 for more details.
See Section 10.7.5, Required Use of Memory Synchronization Instructions, for the conditions when VSYNC is not required before a vector store instruction.

Appendix A
ASCII Character Set

Dec Hex ASCII	Dec Hex ASCII	Dec Hex ASCII	Dec Hex ASCII
00 ₁₀ 00 ₁₆ NUL	32 ₁₀ 20 ₁₆ SP	64 ₁₀ 40 ₁₆ @	96 ₁₀ 60 ₁₆ '
01 ₁₀ 01 ₁₆ SOH	33 ₁₀ 21 ₁₆ !	65 ₁₀ 41 ₁₆ A	97 ₁₀ 61 ₁₆ a
02 ₁₀ 02 ₁₆ STX	34 ₁₀ 22 ₁₆ "	66 ₁₀ 42 ₁₆ B	98 ₁₀ 62 ₁₆ b
03 ₁₀ 03 ₁₆ ETX	35 ₁₀ 23 ₁₆ #	67 ₁₀ 43 ₁₆ C	99 ₁₀ 63 ₁₆ c
04 ₁₀ 04 ₁₆ EOT	36 ₁₀ 24 ₁₆ $	68 ₁₀ 44 ₁₆ D	100 ₁₀ 64 ₁₆ d
05 ₁₀ 05 ₁₆ ENQ	37 ₁₀ 25 ₁₆ %	69 ₁₀ 45 ₁₆ E	101 ₁₀ 65 ₁₆ e
06 ₁₀ 06 ₁₆ ACK	38 ₁₀ 26 ₁₆ &	70 ₁₀ 46 ₁₆ F	102 ₁₀ 66 ₁₆ f
07 ₁₀ 07 ₁₆ BEL	39 ₁₀ 27 ₁₆ '	71 ₁₀ 47 ₁₆ G	103 ₁₀ 67 ₁₆ g
08 ₁₀ 08 ₁₆ BS	40 ₁₀ 28 ₁₆ (	72 ₁₀ 48 ₁₆ H	104 ₁₀ 68 ₁₆ h
09 ₁₀ 09 ₁₆ HT	41 ₁₀ 29 ₁₆ )	73 ₁₀ 49 ₁₆ I	105 ₁₀ 69 ₁₆ i
10 ₁₀ 0A ₁₆ LF	42 ₁₀ 2A ₁₆ *	74 ₁₀ 4A ₁₆ J	106 ₁₀ 6A ₁₆ j
11 ₁₀ 0B ₁₆ VT	43 ₁₀ 2B ₁₆ +	75 ₁₀ 4B ₁₆ K	107 ₁₀ 6B ₁₆ k
12 ₁₀ 0C ₁₆ FF	44 ₁₀ 2C ₁₆ ,	76 ₁₀ 4C ₁₆ l	108 ₁₀ 6C ₁₆ l
13 ₁₀ 0D ₁₆ CR	45 ₁₀ 2D ₁₆ -	77 ₁₀ 4D ₁₆ M	109 ₁₀ 6D ₁₆ m
14 ₁₀ 0E ₁₆ SO	46 ₁₀ 2E ₁₆ .	78 ₁₀ 4E ₁₆ N	110 ₁₀ 6E ₁₆ n
15 ₁₀ 0F ₁₆ SI	47 ₁₀ 2F ₁₆ /	79 ₁₀ 4F ₁₆ O	111 ₁₀ 6F ₁₆ o
16 ₁₀ 10 ₁₆ DLE	48 ₁₀ 30 ₁₆ 0	80 ₁₀ 50 ₁₆ P	112 ₁₀ 70 ₁₆ p
17 ₁₀ 11 ₁₆ DC1	49 ₁₀ 31 ₁₆ 1	81 ₁₀ 51 ₁₆ Q	113 ₁₀ 71 ₁₆ q
18 ₁₀ 12 ₁₆ DC2	50 ₁₀ 32 ₁₆ 2	82 ₁₀ 52 ₁₆ R	114 ₁₀ 72 ₁₆ r
19 ₁₀ 13 ₁₆ DC3	51 ₁₀ 33 ₁₆ 3	83 ₁₀ 53 ₁₆ S	115 ₁₀ 73 ₁₆ s
20 ₁₀ 14 ₁₆ DC4	52 ₁₀ 34 ₁₆ 4	84 ₁₀ 54 ₁₆ T	116 ₁₀ 74 ₁₆ t
21 ₁₀ 15 ₁₆ NAK	53 ₁₀ 35 ₁₆ 5	85 ₁₀ 55 ₁₆ U	117 ₁₀ 75 ₁₆ u
22 ₁₀ 16 ₁₆ SYN	54 ₁₀ 36 ₁₆ 6	86 ₁₀ 56 ₁₆ V	118 ₁₀ 76 ₁₆ v
23 ₁₀ 17 ₁₆ ETB	55 ₁₀ 37 ₁₆ 7	87 ₁₀ 57 ₁₆ W	119 ₁₀ 77 ₁₆ w
24 ₁₀ 18 ₁₆ CAN	56 ₁₀ 38 ₁₆ 8	88 ₁₀ 58 ₁₆ X	120 ₁₀ 78 ₁₆ x
25 ₁₀ 19 ₁₆ EM	57 ₁₀ 39 ₁₆ 9	89 ₁₀ 59 ₁₆ Y	121 ₁₀ 79 ₁₆ y
26 ₁₀ 1A ₁₆ SUB	58 ₁₀ 3A ₁₆ :	90 ₁₀ 5A ₁₆ Z	122 ₁₀ 7A ₁₆ z
27 ₁₀ 1B ₁₆ ESC	59 ₁₀ 3B ₁₆ ;	91 ₁₀ 5B ₁₆ [	123 ₁₀ 7B ₁₆ {
28 ₁₀ 1C ₁₆ FS	60 ₁₀ 3C ₁₆ <	92 ₁₀ 5C ₁₆ \	124 ₁₀ 7C ₁₆ \|
29 ₁₀ 1D ₁₆ GS	61 ₁₀ 3D ₁₆ =	93 ₁₀ 5D ₁₆ ]	125 ₁₀ 7D ₁₆ }
30 ₁₀ 1E ₁₆ RS	62 ₁₀ 3E ₁₆ >	94 ₁₀ 5E ₁₆ ^	126 ₁₀ 7E ₁₆ ~
31 ₁₀ 1F ₁₆ US	63 ₁₀ 3F ₁₆ ?	95 ₁₀ 5F ₁₆ _	127 ₁₀ 7F ₁₆ DEL

Contents

Index

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VAX MACRO and Instruction Set Reference Manual

IOTA

Format

IOTA [/0|1] stride, Vc

Description

10.15 Miscellaneous Instructions

MFVP

Format

{MFVCR|MFVLR|MFVMRLO|MFVMRHI|SYNCH|MSYNCH} dst

Description

MTVP

Format

{MTVCR|MTVLR|MTVMRLO|MTVMRHI} src

Description

VSYNC

Format

VSYNCH

Description

Appendix AASCII Character Set

Appendix A
ASCII Character Set