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Updated: 11 December 1998

VAX MACRO and Instruction Set Reference Manual


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IOTA

Generate Compressed Iota Vector

Format

IOTA [/0|1] stride, Vc

Architecture

Format

opcode cntrl.rw, stride.rl

Opcodes
EDFD IOTA Generate Compressed Iota Vector

vector_control_word


Exceptions


Description

IOTA constructs a vector of offsets for use by the vector gather/scatter instructions VGATH and VSCAT.

IOTA first generates an iota vector of length VLR using the stride operand. An iota vector is a vector whose first element is zero and whose subsequent elements are spaced by the stride increment. The stride can be positive, negative, or zero. For example:


 0*stride, 1*stride, 2*stride, 3*stride, ..., {VLR-1}*stride 

The iota vector is then compressed using the contents of the Vector Mask Register (VMR). Elements of the iota vector for which the corresponding Vector Mask Register bit matches cntrl<MTF> are written in contiguous elements of the destination vector register Vc. Only bits <31:0> of each iota and destination vector element participate in the operation. Bits <63:32> of the destination vector elements are UNPREDICTABLE.

The number of elements written to Vc is returned in the Vector Count Register (VCR). The values of elements in the destination vector register between the new value of VCR and the vector length are UNPREDICTABLE.

Note

If a large value is specified for the stride.rl operand, there is a chance for integer overflow during calculation of the "tmp <- tmp + stride" step. In this case, the overflow is ignored. For example:


tmp  <-  tmp  + stride 
 
Value of tmp before above step:  FFFFFF00 
Value of Stride:                 FFFFFF00 
 
Value of tmp + stride:         1 FFFFFE00 
 
Since the overflow is ignored, the new value of tmp 
is FFFFFE00. 

10.15 Miscellaneous Instructions

This section describes VAX vector architecture miscellaneous instructions.


MFVP

Move from Vector Processor

Format


{MFVCR|MFVLR|MFVMRLO|MFVMRHI|SYNCH|MSYNCH} dst

Architecture

Format

opcode regnum.rw, dst.wl

Opcodes
31FD MFVP Move from Vector Processor

vector_control_word

None.

Exceptions

MFVP instructions that specify reserved values of the regnum operand produce UNPREDICTABLE results.


Description

This instruction can be used to read the Vector Count, Length, and Mask Registers, and to synchronize a scalar processor with its associated vector processor.

When the scalar processor issues an MFVP instruction to the vector processor, the scalar processor waits for the MFVP result to be written before processing other instructions.

MFVP from VCR or VLR does not read that register until all previous write operations to the register are completed. MFVP from VMR<31:0> or VMR<63:32> does not read that longword of VMR until all previous write operations to the same longword of VMR are completed; however, this is not true for previous write operations to the other longword.

SYNC allows software to ensure that the unreported exceptions of all previously issued vector instructions (including vector memory instructions in asynchronous memory management mode) are detected and reported to the scalar processor before the scalar processor proceeds with further instructions. For more details about SYNC and its exception reporting nature refer to Section 10.7.1, Scalar/Vector Instruction Synchronization.

MSYNC allows software to ensure that all previously issued memory instructions of the scalar/vector processor pair are complete before the scalar processor proceeds with further instructions. For more details about MSYNC and its exception reporting nature, refer to Section 10.7.2, Memory Instruction Synchronization.

The value of the vector control register (VCR, VLR, VMR<31:0>, VMR<63:32>) delivered by an MFVP depends upon the value of certain vector register elements and vector control register bits. Unreported exceptions that occur in the production of these elements and control register bits are reported by the vector processor prior to the completion of the MFVP from the vector control register.

In addition, there are vector register elements and vector control register bits that the value of a vector control register delivered by an MFVP does not depend upon. It is UNPREDICTABLE whether unreported exceptions that occur in the production of these elements and control register bits are reported by the vector processor prior to the completion of the MFVP from the vector control register. Software must not rely upon the reporting of these exceptions prior to the completion of the MFVP for the correctness of program results.

Section 10.5.3.3, Dependencies Among Vector Results, gives the necessary rules to determine what vector control register elements and vector control register bits the value of a vector control register delivered by an MFVP depends upon. Examples of MFVP exception reporting using these rules are found in Section 10.6.5.

When a vector arithmetic exception or memory management exception (in asynchronous memory management mode) is reported prior to the completion of an MFVP, the following occur:

After the appropriate fault has been serviced, the MFVP may be returned to through an REI. If both exception conditions are encountered by an MFVP, then the MFVP itself takes a vector processor disabled fault. In this case, after the vector processor disabled fault has been serviced, returning to the MFVP instruction will cause the asynchronous memory management exception to be reported.


MTVP

Move to Vector Processor

Format


{MTVCR|MTVLR|MTVMRLO|MTVMRHI} src

Architecture

Format

opcode regnum.rw, src.rl

Opcodes
A9FD MTVP Move to Vector Processor

vector_control_word

None.

Exceptions

Move to Vector Processor instructions that specify reserved values of the regnum operand produce UNPREDICTABLE results.


Description

This instruction can be used to write the Vector Count, Length, and Mask Registers.

The new value of VCR, VLR, or VMR does not affect any prior instructions. The new value remains in effect for all subsequent vector instructions executed until a new value is loaded.


VSYNC

Synchronize Vector Memory Access

Format

VSYNCH

Architecture

Format

opcode regnum.rw

Opcodes
A8FD VSYNC Synchronize Vector Memory Access

vector_control_word

None.

Exceptions

Synchronize Vector Memory Access instructions that specify reserved values of the regnum operand produce UNPREDICTABLE results.


Description

The VSYNC instruction can be used to synchronize memory access within the vector processor. The instruction allows software to order the conflicting memory accesses of vector-memory instructions issued after VSYNC with those of vector-memory instructions issued before VSYNC. Specifically, VSYNC forces the access of a memory location by any subsequent vector-memory instruction to wait for (depend upon) the completion of all prior conflicting accesses of that location by previous vector-memory instructions. See Section 10.7.1 for more details.

See Section 10.7.5, Required Use of Memory Synchronization Instructions, for the conditions when VSYNC is not required before a vector store instruction.


Appendix A
ASCII Character Set

Dec Hex ASCII Dec Hex ASCII Dec Hex ASCII Dec Hex ASCII
00 10 00 16 NUL 32 10 20 16 SP 64 10 40 16 @ 96 10 60 16 '
01 10 01 16 SOH 33 10 21 16 ! 65 10 41 16 A 97 10 61 16 a
02 10 02 16 STX 34 10 22 16 " 66 10 42 16 B 98 10 62 16 b
03 10 03 16 ETX 35 10 23 16 # 67 10 43 16 C 99 10 63 16 c
04 10 04 16 EOT 36 10 24 16 $ 68 10 44 16 D 100 10 64 16 d
05 10 05 16 ENQ 37 10 25 16 % 69 10 45 16 E 101 10 65 16 e
06 10 06 16 ACK 38 10 26 16 & 70 10 46 16 F 102 10 66 16 f
07 10 07 16 BEL 39 10 27 16 ' 71 10 47 16 G 103 10 67 16 g
08 10 08 16 BS 40 10 28 16 ( 72 10 48 16 H 104 10 68 16 h
09 10 09 16 HT 41 10 29 16 ) 73 10 49 16 I 105 10 69 16 i
10 10 0A 16 LF 42 10 2A 16 * 74 10 4A 16 J 106 10 6A 16 j
11 10 0B 16 VT 43 10 2B 16 + 75 10 4B 16 K 107 10 6B 16 k
12 10 0C 16 FF 44 10 2C 16 , 76 10 4C 16 l 108 10 6C 16 l
13 10 0D 16 CR 45 10 2D 16 - 77 10 4D 16 M 109 10 6D 16 m
14 10 0E 16 SO 46 10 2E 16 . 78 10 4E 16 N 110 10 6E 16 n
15 10 0F 16 SI 47 10 2F 16 / 79 10 4F 16 O 111 10 6F 16 o
16 10 10 16 DLE 48 10 30 16 0 80 10 50 16 P 112 10 70 16 p
17 10 11 16 DC1 49 10 31 16 1 81 10 51 16 Q 113 10 71 16 q
18 10 12 16 DC2 50 10 32 16 2 82 10 52 16 R 114 10 72 16 r
19 10 13 16 DC3 51 10 33 16 3 83 10 53 16 S 115 10 73 16 s
20 10 14 16 DC4 52 10 34 16 4 84 10 54 16 T 116 10 74 16 t
21 10 15 16 NAK 53 10 35 16 5 85 10 55 16 U 117 10 75 16 u
22 10 16 16 SYN 54 10 36 16 6 86 10 56 16 V 118 10 76 16 v
23 10 17 16 ETB 55 10 37 16 7 87 10 57 16 W 119 10 77 16 w
24 10 18 16 CAN 56 10 38 16 8 88 10 58 16 X 120 10 78 16 x
25 10 19 16 EM 57 10 39 16 9 89 10 59 16 Y 121 10 79 16 y
26 10 1A 16 SUB 58 10 3A 16 : 90 10 5A 16 Z 122 10 7A 16 z
27 10 1B 16 ESC 59 10 3B 16 ; 91 10 5B 16 [ 123 10 7B 16 {
28 10 1C 16 FS 60 10 3C 16 < 92 10 5C 16 \ 124 10 7C 16 |
29 10 1D 16 GS 61 10 3D 16 = 93 10 5D 16 ] 125 10 7D 16 }
30 10 1E 16 RS 62 10 3E 16 > 94 10 5E 16 ^ 126 10 7E 16 ~
31 10 1F 16 US 63 10 3F 16 ? 95 10 5F 16 _ 127 10 7F 16 DEL


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