OpenVMS Alpha System Analysis Tools Manual

Updated: 11 December 1998

OpenVMS Alpha System Analysis Tools Manual

Contents

Index

SHOW SPINLOCKS

Displays the multiprocessing synchronization data structures.

Format

SHOW SPINLOCKS {[name]|/ADDRESS=expression|/INDEX=expression} [/OWNED|/DYNAMIC|/STATIC] [{/BRIEF|/FULL}]

Parameter

name
Name of the spin lock, fork lock, or device lock structure to be displayed. Device lock names are of the form [node$]lock, where node optionally indicates the OpenVMS Cluster node name (allocation class) and lock indicates the device and controller identification (for example, HAETAR$DUA).

Qualifiers

/ADDRESS=expression
Displays the lock at the address specified in expression. You can use the /ADDRESS qualifier to display a specific device lock; however, the name of the device lock is listed as "Unknown" in the display.
/BRIEF
Produces a condensed display of the lock information displayed by default by the SHOW SPINLOCKS command, including the following: address, spinlock name or device name, IPL or device IPL, rank, index, ownership depth, number of waiting CPUs, CPU ID of the owner CPU, and interlock status (depth of ownership).
/DYNAMIC
Displays information for all device locks in the system.
/FULL
Displays full descriptive and diagnostic information for each displayed spin lock, fork lock, or device lock.
/INDEX=expression
Displays the system spin lock whose index is specified in expression. You cannot use the /INDEX qualifier to display a device lock.
/OWNED
Displays information for all spin locks, fork locks, and device locks owned by the SDA current CPU. If a processor does not own any spin locks, SDA displays the following message:
No spinlocks currently owned by CPU xx
The xx represents the CPU ID of the processor.
/STATIC
Displays information for all system spin locks and fork locks.

Description

The SHOW SPINLOCKS command displays status and diagnostic information about the multiprocessing synchronization structures known as spin locks.
A static spin lock is a spin lock whose data structure is permanently assembled into the system. Static spin locks are accessed as indexes into a vector of longword addresses called the spin lock vector, the address of which is contained in SMP$AR_SPNLKVEC. System spin locks and fork locks are static spin locks. Table 4-23 lists the static spin locks.
A dynamic spin lock is a spin lock that is created based on the configuration of a particular system. One such dynamic spin lock is the device lock SYSMAN creates when configuring a particular device. This device lock synchronizes access to the device's registers and certain UCB fields. The system creates a dynamic spin lock by allocating space from nonpaged pool, rather than assembling the lock into the system as it does in creating a static spin lock.
See the Writing OpenVMS Alpha Device Drivers in C for a full discussion of the role of spin locks in maintaining synchronization of kernel mode activities in a multiprocessing environment.

Table 4-23 Static Spin Locks
Name Description

QUEUEAST Fork lock for queuing ASTs at IPL 6

FILSYS Lock on file system structures

LCKMGR Lock on all lock manager structures

IOLOCK8/SCS Fork lock for executing a driver fork process at IPL 8

TX_SYNCH Transaction processing lock

TIMER Lock for adding and deleting timer queue entries and searching the timer queue

PORT Template structure for dynamic spinlocks for ports with multiple devices

IO_MISC Miscellaneous short term I/O locks

MMG Lock on memory management, PFN database, swapper, modified page writer, and creation of per-CPU database structures

SCHED Lock on process control blocks (PCBs), scheduler database, and mutex acquisition and release structures

IOLOCK9 Fork lock for executing a driver fork process at IPL 9

IOLOCK10 Fork lock for executing a driver fork process at IPL 10

IOLOCK11 Fork lock for executing a driver fork process at IPL 11

MAILBOX Lock for sending messages to mailboxes

POOL Lock on nonpaged pool database

PERFMON Lock for I/O performance monitoring

INVALIDATE Lock for system space translation buffer (TB) invalidation

HWCLK Lock on hardware clock database, including the quadword containing the due time of the first timer queue entry (EXE$GQ_1ST_TIME) and the quadword containing the system time (EXE$GQ_SYSTIME)

MEGA Lock for serializing access to fork-wait queue

EMB/MCHECK Lock for allocating and releasing error-logging buffers and synchronizing certain machine error handling

For each spin lock, fork lock, or device lock in the system, SHOW SPINLOCKS provides the following information:

Name of the spin lock (or device name for the device lock)
Address of the spinlock data structure (SPL)
The owner CPU's CPU ID
IPL at which allocation of the lock is synchronized on a local processor
Number of nested acquisitions of the spin lock by the processor owning the spin lock ("Ownership Depth")
Rank of the spin lock
Number of processors waiting to obtain the spin lock
Spinlock index (for static spin locks only)
Timeout interval for spinlock acquisition (in terms of 10 milliseconds)

SHOW SPINLOCKS/BRIEF produces a condensed display of this same information.
If the system under analysis was executing with full-checking multiprocessing enabled (according to the setting of the MULTIPROCESSING system parameter), SHOW SPINLOCKS/FULL adds to the spinlock display the last eight PCs at which the lock was acquired or released. If applicable, SDA also displays the PC of the last release of multiple, nested acquisitions of the lock.
If no spin lock name, address, or index is given, then information is displayed for all applicable spin locks.

**Table 4-23 Static Spin Locks**
Name	Description
QUEUEAST	Fork lock for queuing ASTs at IPL 6
FILSYS	Lock on file system structures
LCKMGR	Lock on all lock manager structures
IOLOCK8/SCS	Fork lock for executing a driver fork process at IPL 8
TX_SYNCH	Transaction processing lock
TIMER	Lock for adding and deleting timer queue entries and searching the timer queue
PORT	Template structure for dynamic spinlocks for ports with multiple devices
IO_MISC	Miscellaneous short term I/O locks
MMG	Lock on memory management, PFN database, swapper, modified page writer, and creation of per-CPU database structures
SCHED	Lock on process control blocks (PCBs), scheduler database, and mutex acquisition and release structures
IOLOCK9	Fork lock for executing a driver fork process at IPL 9
IOLOCK10	Fork lock for executing a driver fork process at IPL 10
IOLOCK11	Fork lock for executing a driver fork process at IPL 11
MAILBOX	Lock for sending messages to mailboxes
POOL	Lock on nonpaged pool database
PERFMON	Lock for I/O performance monitoring
INVALIDATE	Lock for system space translation buffer (TB) invalidation
HWCLK	Lock on hardware clock database, including the quadword containing the due time of the first timer queue entry (EXE$GQ_1ST_TIME) and the quadword containing the system time (EXE$GQ_SYSTIME)
MEGA	Lock for serializing access to fork-wait queue
EMB/MCHECK	Lock for allocating and releasing error-logging buffers and synchronizing certain machine error handling

Examples

#1
SDA> SHOW SPINLOCKS System static spinlock structures --------------------------------- EMB Address 80424480 Owner CPU ID None DIPL 0000001F Ownership Depth 00000000 Rank 00000000 CPUs Waiting 00000000 Index 00000020 Timeout Interval 000186A0 EMB Address 80424480 Owner CPU ID None DIPL 0000001F Ownership Depth 00000000 Rank 00000000 CPUs Waiting 00000000 Index 00000020 Timeout Interval 000186A0 MEGA Address 80424500 Owner CPU ID None DIPL 00000016 Ownership Depth 00000000 Rank 00000002 CPUs Waiting 00000000 Index 00000022 Timeout Interval 000186A0 HWCLK Address 80424580 Owner CPU ID None DIPL 00000016 Ownership Depth 00000000 Rank 00000004 CPUs Waiting 00000000 Index 00000024 Timeout Interval 000186A0 . . . System dynamic spinlock structures ---------------------------------- OPA Address 8041E880 Owner CPU ID None DIPL 00000014 Ownership Depth 00000000 Rank FFFFFFFF CPUs Waiting 00000000 Timeout Interval 000186A0 MBA Address 80424780 Owner CPU ID None DIPL 0000000B Ownership Depth 00000000 Rank 0000000C CPUs Waiting 00000000 Index 0000002C Timeout Interval 000186A0 NLA Address 80424780 Owner CPU ID None DIPL 0000000B Ownership Depth 00000000 Rank 0000000C CPUs Waiting 00000000 Index 0000002C Timeout Interval 000186A0 PKI Address 80552800 Owner CPU ID None DIPL 00000014 Ownership Depth 00000000 Rank FFFFFFFF CPUs Waiting 00000000 Timeout Interval 000186A0 . . .

SDA> SHOW SPINLOCKS
System static spinlock structures
---------------------------------
EMB                                Address   80424480
Owner CPU ID           None        DIPL      0000001F
Ownership Depth    00000000        Rank      00000000
CPUs Waiting       00000000        Index     00000020
Timeout Interval   000186A0
  
EMB                                Address   80424480
Owner CPU ID           None        DIPL      0000001F
Ownership Depth    00000000        Rank      00000000
CPUs Waiting       00000000        Index     00000020
Timeout Interval   000186A0
  
MEGA                               Address   80424500
Owner CPU ID           None        DIPL      00000016
Ownership Depth    00000000        Rank      00000002
CPUs Waiting       00000000        Index     00000022
Timeout Interval   000186A0
  
HWCLK                              Address   80424580
Owner CPU ID           None        DIPL      00000016
Ownership Depth    00000000        Rank      00000004
CPUs Waiting       00000000        Index     00000024
Timeout Interval   000186A0
  
   .
   .
   .
System dynamic spinlock structures
----------------------------------
OPA                                Address   8041E880
Owner CPU ID           None        DIPL      00000014
Ownership Depth    00000000        Rank      FFFFFFFF
CPUs Waiting       00000000
Timeout Interval   000186A0
  
MBA                                Address   80424780
Owner CPU ID           None        DIPL      0000000B
Ownership Depth    00000000        Rank      0000000C
CPUs Waiting       00000000        Index     0000002C
Timeout Interval   000186A0
  
NLA                                Address   80424780
Owner CPU ID           None        DIPL      0000000B
Ownership Depth    00000000        Rank      0000000C
CPUs Waiting       00000000        Index     0000002C
Timeout Interval   000186A0
  
PKI                                Address   80552800
Owner CPU ID           None        DIPL      00000014
Ownership Depth    00000000        Rank      FFFFFFFF
CPUs Waiting       00000000
Timeout Interval   000186A0
  
   .
   .
   .

This excerpt illustrates the default output of the SHOW SPINLOCKS command.

#2
SDA> SHOW SPINLOCKS/BRIEF Address Spnlck Name IPL Rank Index Depth #Waiting Ownr CPU Interlock ---------------------------------------------------------------------------- 8041F400 EMB 001F 00000000 00000020 00000000 00000000 None Free 8041F400 EMB 001F 00000000 00000020 00000000 00000000 None Free 8041F480 MEGA 001F 00000002 00000022 00000000 00000000 None Free 8041F500 HWCLK 0016 00000004 00000024 00000000 00000000 None Free 8041F580 INVALIDATE 0015 00000006 00000026 00000000 00000000 None Free 8041F600 PERFMON 000F 00000008 00000028 00000000 00000000 None Free 8041F680 POOL 000B 0000000A 0000002A 00000000 00000000 None Free 8041F700 MAILBOX 000B 0000000C 0000002C 00000000 00000000 None Free 8041F780 IOLOCK11 000B 0000000E 0000002E 00000000 00000000 None Free 8041F800 IOLOCK10 000A 0000000F 0000002F 00000000 00000000 None Free 8041F880 IOLOCK9 0009 00000010 00000030 00000000 00000000 None Free 8041F900 SCHED 0008 00000012 00000032 00000000 00000000 None Free 8041F980 MMG 0008 00000014 00000034 00000000 00000000 None Free 8041FA00 IO_MISC 0008 00000016 00000036 00000000 00000000 None Free 8041FA80 TIMER 0008 00000018 00000038 00000000 00000000 None Free 8041FB00 TX_SYNCH 0008 00000019 00000039 00000000 00000000 None Free 8041FB80 SCS 0008 0000001A 0000003A 00000000 00000000 None Free 8041FC00 FILSYS 0008 0000001C 0000003C 00000000 00000000 None Free 8041FC80 QUEUEAST 0006 0000001E 0000003E 00000000 00000000 None Free 80419880 PIPERA$OPA 0015 FFFFFFFF 00000000 00000000 None Free 8041F700 PIPERA$MBA 000B 0000000C 0000002C 00000000 00000000 None Free 8041F700 PIPERA$NLA 000B 0000000C 0000002C 00000000 00000000 None Free 805E9900 PIPERA$DKB 0016 FFFFFFFF 00000000 00000000 None Free 805E9E80 PIPERA$PKB 0015 FFFFFFFF 00000000 00000000 None Free 8041FB80 PIPERA$FTA 0008 0000001A 0000003A 00000000 00000000 None Free 805B9400 PIPERA$PKA 0015 FFFFFFFF 00000000 00000000 None Free 805BBC00 PIPERA$DKA 0016 FFFFFFFF 00000000 00000000 None Free 805BC780 PIPERA$ESA 0015 FFFFFFFF 00000000 00000000 None Free 805BE080 PIPERA$TTA 0015 FFFFFFFF 00000000 00000000 None Free 805BEB00 PIPERA$SOA 0015 FFFFFFFF 00000000 00000000 None Free 8041FB80 PIPERA$NET 0008 0000001A 0000003A 00000000 00000000 None Free 8041FB80 PIPERA$NDA 0008 0000001A 0000003A 00000000 00000000 None Free 8041FB80 PIPERA$RTA 0008 0000001A 0000003A 00000000 00000000 None Free 8041FB80 PIPERA$RTB 0008 0000001A 0000003A 00000000 00000000 None Free 8041FB80 PIPERA$LTA 0008 0000001A 0000003A 00000000 00000000 None Free 8041FB80 PIPERA$RTC 0008 0000001A 0000003A 00000000 00000000 None Free 8041FB80 PIPERA$PDA 0008 0000001A 0000003A 00000000 00000000 None Free

SDA> SHOW SPINLOCKS/BRIEF
Address  Spnlck Name  IPL   Rank     Index    Depth  #Waiting Ownr CPU Interlock
 
----------------------------------------------------------------------------
8041F400 EMB         001F 00000000 00000020 00000000 00000000   None     Free
8041F400 EMB         001F 00000000 00000020 00000000 00000000   None     Free
8041F480 MEGA        001F 00000002 00000022 00000000 00000000   None     Free
8041F500 HWCLK       0016 00000004 00000024 00000000 00000000   None     Free
8041F580 INVALIDATE  0015 00000006 00000026 00000000 00000000   None     Free
8041F600 PERFMON     000F 00000008 00000028 00000000 00000000   None     Free
8041F680 POOL        000B 0000000A 0000002A 00000000 00000000   None     Free
8041F700 MAILBOX     000B 0000000C 0000002C 00000000 00000000   None     Free
8041F780 IOLOCK11    000B 0000000E 0000002E 00000000 00000000   None     Free
8041F800 IOLOCK10    000A 0000000F 0000002F 00000000 00000000   None     Free
8041F880 IOLOCK9     0009 00000010 00000030 00000000 00000000   None     Free
8041F900 SCHED       0008 00000012 00000032 00000000 00000000   None     Free
8041F980 MMG         0008 00000014 00000034 00000000 00000000   None     Free
8041FA00 IO_MISC     0008 00000016 00000036 00000000 00000000   None     Free
8041FA80 TIMER       0008 00000018 00000038 00000000 00000000   None     Free
8041FB00 TX_SYNCH    0008 00000019 00000039 00000000 00000000   None     Free
8041FB80 SCS         0008 0000001A 0000003A 00000000 00000000   None     Free
8041FC00 FILSYS      0008 0000001C 0000003C 00000000 00000000   None     Free
8041FC80 QUEUEAST    0006 0000001E 0000003E 00000000 00000000   None     Free
80419880 PIPERA$OPA  0015 FFFFFFFF          00000000 00000000   None     Free
8041F700 PIPERA$MBA  000B 0000000C 0000002C 00000000 00000000   None     Free
8041F700 PIPERA$NLA  000B 0000000C 0000002C 00000000 00000000   None     Free
805E9900 PIPERA$DKB  0016 FFFFFFFF          00000000 00000000   None     Free
805E9E80 PIPERA$PKB  0015 FFFFFFFF          00000000 00000000   None     Free
8041FB80 PIPERA$FTA  0008 0000001A 0000003A 00000000 00000000   None     Free
805B9400 PIPERA$PKA  0015 FFFFFFFF          00000000 00000000   None     Free
805BBC00 PIPERA$DKA  0016 FFFFFFFF          00000000 00000000   None     Free
805BC780 PIPERA$ESA  0015 FFFFFFFF          00000000 00000000   None     Free
805BE080 PIPERA$TTA  0015 FFFFFFFF          00000000 00000000   None     Free
805BEB00 PIPERA$SOA  0015 FFFFFFFF          00000000 00000000   None     Free
8041FB80 PIPERA$NET  0008 0000001A 0000003A 00000000 00000000   None     Free
8041FB80 PIPERA$NDA  0008 0000001A 0000003A 00000000 00000000   None     Free
8041FB80 PIPERA$RTA  0008 0000001A 0000003A 00000000 00000000   None     Free
8041FB80 PIPERA$RTB  0008 0000001A 0000003A 00000000 00000000   None     Free
8041FB80 PIPERA$LTA  0008 0000001A 0000003A 00000000 00000000   None     Free
8041FB80 PIPERA$RTC  0008 0000001A 0000003A 00000000 00000000   None     Free
8041FB80 PIPERA$PDA  0008 0000001A 0000003A 00000000 00000000   None     Free

This excerpt illustrates the condensed form of the display produced in the first example.

SHOW STACK

Displays the location and contents of the process stacks (of the SDA current process) and the system stack.

Format

SHOW STACK {range|/ALL|[/EXECUTIVE|/INTERRUPT|/KERNEL |/PHYSICAL|/SUPERVISOR|/SYSTEM|/USER]} {/LONG|/QUAD (d)}

Parameter

range
Range of memory locations you want to display in stack format. You can express a range using the following syntax:

m:n Range of addresses from m to n

m;n Range of addresses starting at m and continuing for n bytes

Qualifiers

/ALL
Displays the locations and contents of the four process stacks for the current SDA process and the system stack.
/EXECUTIVE
Shows the executive stack for the SDA current process.
/INTERRUPT
The interrupt stack does not exist in OpenVMS Alpha. This qualifier shows the system stack and is retained for compatibility with OpenVMS VAX.
/KERNEL
Shows the kernel stack for the SDA current process.
/LONG
Displays longword width stacks. If this qualifier is not specified, SDA by default displays quadword width stacks.
/PHYSICAL
Treats the start and/or end addresses in the given range as physical addresses. This qualifier is only relevant when a range is specified. By default, SDA treats range addresses as virtual addresses.
/QUAD
Displays quadword width stacks. This is the default.
/SUPERVISOR
Shows the supervisor stack for the SDA current process.
/SYSTEM
Shows the system stack.
/USER
Shows the user stack for the SDA current process.

Description

The SHOW STACK command, by default, displays the stack that was in use when the system failed, or, in the analysis of a running system, the current operating stack. For a process that became the SDA current process, as the result of a SET PROCESS command, the SHOW STACK command by default shows its current operating stack.
The various qualifiers to the command can display any of the four per-process stacks for the SDA current process, as well as the system stack for the SDA current CPU.
You can define SDA process and CPU context by using the SET CPU, SHOW CPU, SHOW CRASH, SET PROCESS, and SHOW PROCESS commands as indicated in their command descriptions. A complete discussion of SDA context control appears in Chapter 2, Section 2.5.
SDA provides the following information in each stack display:

Section Contents

Identity of stack SDA indicates whether the stack is a process stack (user, supervisor, executive, or kernel) or the system stack.

Stack pointer The stack pointer identifies the top of the stack. The display indicates the stack pointer by the symbol SP =>.

Stack address SDA lists all the addresses that the operating system has allocated to the stack. The stack addresses are listed in a column that increases in increments of 8 bytes (one quadword), unless you specify the /LONG qualifier in which case addresses are listed in increments of 4 (one longword).

Stack contents SDA lists the contents of the stack in a column to the right of the stack addresses.

Symbols SDA attempts to display the contents of a location symbolically, using a symbol and an offset.
If the address cannot be symbolized, this column is left blank.

Canonical stack When displaying the kernel stack of a noncurrent process in a crash dump, SDA identifies the stack locations used by the scheduler to store the register contents of the process.

If a stack is empty, the display shows the following:
SP => (STACK IS EMPTY)

Section	Contents
Identity of stack	SDA indicates whether the stack is a process stack (user, supervisor, executive, or kernel) or the system stack.
Stack pointer	The stack pointer identifies the top of the stack. The display indicates the stack pointer by the symbol SP =>.
Stack address	SDA lists all the addresses that the operating system has allocated to the stack. The stack addresses are listed in a column that increases in increments of 8 bytes (one quadword), unless you specify the /LONG qualifier in which case addresses are listed in increments of 4 (one longword).
Stack contents	SDA lists the contents of the stack in a column to the right of the stack addresses.
Symbols	SDA attempts to display the contents of a location symbolically, using a symbol and an offset. If the address cannot be symbolized, this column is left blank.
Canonical stack	When displaying the kernel stack of a noncurrent process in a crash dump, SDA identifies the stack locations used by the scheduler to store the register contents of the process.

Example


SDA> SHOW STACK Current Operating Stack (SYSTEM): FFFFFFFF.8244BD08 FFFFFFFF.800600FC SCH$REPORT_EVENT_C+000FC FFFFFFFF.8244BD10 00000000.00000002 FFFFFFFF.8244BD18 00000000.00000005 FFFFFFFF.8244BD20 FFFFFFFF.8060C7C0 SP => FFFFFFFF.8244BD28 FFFFFFFF.8244BEE8 FFFFFFFF.8244BD30 FFFFFFFF.80018960 EXE$HWCLKINT_C+00260 FFFFFFFF.8244BD38 00000000.000001B8 FFFFFFFF.8244BD40 00000000.00000050 FFFFFFFF.8244BD48 00000000.00000210 UCB$N_RSID+00002 FFFFFFFF.8244BD50 00000000.00000000 FFFFFFFF.8244BD58 00000000.00000000 FFFFFFFF.8244BD60 FFFFFFFF.804045D0 SCH$GQ_IDLE_CPUS FFFFFFFF.8244BD68 FFFFFFFF.8041A340 EXE$GL_FKWAITFL+00020 FFFFFFFF.8244BD70 00000000.00000250 UCB$T_MSGDATA+00034 FFFFFFFF.8244BD78 00000000.00000001 CHF$IS_MCH_ARGS FFFFFFFF.8244BD80 00000000.0000002B CHF$PH_MCH_FRAME FFFFFFFF.8244BD88 FFFFFFFF.8244BFB0 CHF$IS_MCH_DEPTH FFFFFFFF.8244BD90 80000000.FFFFFFFD G CHF$PH_MCH_DADDR FFFFFFFF.8244BD98 00000000.00001600 CTL$C_CLIDATASZ+00060 CHF$PH_MCH_ESF_ADDR FFFFFFFF.8244BDA0 FFFFFFFF.8244BF40 CHF$PH_MCH_SIG_ADDR FFFFFFFF.8244BDA8 FFFFFFFF.8244BEE8 CHF$IH_MCH_SAVR0 FFFFFFFF.8244BDB0 FFFFFFFF.8041FB00 SMP$RELEASEL+00640 CHF$IH_MCH_SAVR1 FFFFFFFF.8244BDB8 00000000.00000000 CHF$IH_MCH_SAVR16 FFFFFFFF.8244BDC0 00000000.0000000D CHF$IH_MCH_SAVR17 FFFFFFFF.8244BDC8 0000FFF0.00007E04 CHF$IH_MCH_SAVR18 FFFFFFFF.8244BDD0 00000000.00000000 CHF$IH_MCH_SAVR19 FFFFFFFF.8244BDD8 00000000.00000001 CHF$IH_MCH_SAVR20 FFFFFFFF.8244BDE0 00000000.00000000 CHF$IH_MCH_SAVR21 FFFFFFFF.8244BDE8 FFFFFFFF.805AE4B6 SISR+0006E CHF$IH_MCH_SAVR22 FFFFFFFF.8244BDF0 00000000.00000001 CHF$IH_MCH_SAVR23 FFFFFFFF.8244BDF8 00000000.00000010 CHF$IH_MCH_SAVR24 FFFFFFFF.8244BE00 00000000.00000008 CHF$IH_MCH_SAVR25 FFFFFFFF.8244BE08 00000000.00000010 CHF$IH_MCH_SAVR26 FFFFFFFF.8244BE10 00000000.00000001 CHF$IH_MCH_SAVR27 FFFFFFFF.8244BE18 00000000.00000000 CHF$IH_MCH_SAVR28 FFFFFFFF.8244BE20 FFFFFFFF.804045D0 SCH$GQ_IDLE_CPUS FFFFFFFF.8244BE28 30000000.00000300 UCB$L_PI_SVA FFFFFFFF.8244BE30 FFFFFFFF.80040F6C EXE$REFLECT_C+00950 FFFFFFFF.8244BE38 18000000.00000300 UCB$L_PI_SVA FFFFFFFF.8244BE40 FFFFFFFF.804267A0 EXE$CONTSIGNAL+00228 FFFFFFFF.8244BE48 00000000.7FFD00A8 PIO$GW_IIOIMPA FFFFFFFF.8244BE50 00000003.00000000 FFFFFFFF.8244BE58 FFFFFFFF.8003FC20 EXE$CONNECT_SERVICES_C+00920 FFFFFFFF.8244BE60 FFFFFFFF.8041FB00 SMP$RELEASEL+00640 FFFFFFFF.8244BE68 00000000.00000000 FFFFFFFF.8244BE70 FFFFFFFF.8042CD50 SCH$WAIT_PROC+00060 FFFFFFFF.8244BE78 00000000.0000000D FFFFFFFF.8244BE80 0000FFF0.00007E04 FFFFFFFF.8244BE88 00000000.00000000 FFFFFFFF.8244BE90 00000000.00000001 FFFFFFFF.8244BE98 00000000.00000000 FFFFFFFF.8244BEA0 FFFFFFFF.805AE4B6 SISR+0006E FFFFFFFF.8244BEA8 00000000.00000001 FFFFFFFF.8244BEB0 00000000.00000010 FFFFFFFF.8244BEB8 00000000.00000008 FFFFFFFF.8244BEC0 00000000.00000010 FFFFFFFF.8244BEC8 00000000.00000001 FFFFFFFF.8244BED0 00000000.00000000 FFFFFFFF.8244BED8 FFFFFFFF.804045D0 SCH$GQ_IDLE_CPUS FFFFFFFF.8244BEE0 00000000.00000001 CHF$L_SIG_ARGS FFFFFFFF.8244BEE8 0000000C.00000005 CHF$L_SIG_ARG1 FFFFFFFF.8244BEF0 FFFFFFFC.00010000 SYS$K_VERSION_08 FFFFFFFF.8244BEF8 00000300.FFFFFFFC UCB$L_PI_SVA FFFFFFFF.8244BF00 00000002.00000001 FFFFFFFF.8244BF08 00000000.0000000C FFFFFFFF.8244BF10 00000000.00000000 FFFFFFFF.8244BF18 00000000.FFFFFFFC FFFFFFFF.8244BF20 00000008.00000000 FFFFFFFF.8244BF28 00000000.00000001 FFFFFFFF.8244BF30 00000008.00000000 FFFFFFFF.8244BF38 00000000.FFFFFFFC INTSTK$Q_R2 FFFFFFFF.8244BF40 FFFFFFFF.80404668 SCH$GL_ACTIVE_PRIORITY INTSTK$Q_R3 FFFFFFFF.8244BF48 FFFFFFFF.8042F280 SCH$WAIT_KERNEL_MODE INTSTK$Q_R4 FFFFFFFF.8244BF50 FFFFFFFF.80615F00 INTSTK$Q_R5 FFFFFFFF.8244BF58 00000000.00000000 INTSTK$Q_R6 FFFFFFFF.8244BF60 FFFFFFFF.805AE000 INTSTK$Q_R7 FFFFFFFF.8244BF68 00000000.00000000 INTSTK$Q_PC FFFFFFFF.8244BF70 00000000.FFFFFFFC INTSTK$Q_PS FFFFFFFF.8244BF78 30000000.00000300 UCB$L_PI_SVA FFFFFFFF.8244BF80 FFFFFFFF.80404668 SCH$GL_ACTIVE_PRIORITY FFFFFFFF.8244BF88 00000000.7FFD00A8 PIO$GW_IIOIMPA FFFFFFFF.8244BF90 00000000.00000000 FFFFFFFF.8244BF98 FFFFFFFF.8042CD50 SCH$WAIT_PROC+00060 FFFFFFFF.8244BFA0 00000000.00000044 FFFFFFFF.8244BFA8 FFFFFFFF.80403C30 SMP$GL_FLAGS Prev SP (8244BFB0) => FFFFFFFF.8244BFB0 FFFFFFFF.8042CD50 SCH$WAIT_PROC+00060 FFFFFFFF.8244BFB8 00000000.00000000 FFFFFFFF.8244BFC0 FFFFFFFF.805EE040 FFFFFFFF.8244BFC8 FFFFFFFF.8006DB54 PROCESS_MANAGEMENT_NPRO+0DB54 FFFFFFFF.8244BFD0 FFFFFFFF.80404668 SCH$GL_ACTIVE_PRIORITY FFFFFFFF.8244BFD8 FFFFFFFF.80615F00 FFFFFFFF.8244BFE0 FFFFFFFF.8041B220 SCH$RESOURCE_WAIT FFFFFFFF.8244BFE8 00000000.00000044 FFFFFFFF.8244BFF0 FFFFFFFF.80403C30 SMP$GL_FLAGS FFFFFFFF.8244BFF8 00000000.7FF95E00

SDA> SHOW STACK
 
Current Operating Stack (SYSTEM):
                       FFFFFFFF.8244BD08  FFFFFFFF.800600FC  SCH$REPORT_EVENT_C+000FC
                       FFFFFFFF.8244BD10  00000000.00000002  
                       FFFFFFFF.8244BD18  00000000.00000005  
                       FFFFFFFF.8244BD20  FFFFFFFF.8060C7C0  
                SP =>  FFFFFFFF.8244BD28  FFFFFFFF.8244BEE8  
                       FFFFFFFF.8244BD30  FFFFFFFF.80018960  EXE$HWCLKINT_C+00260
                       FFFFFFFF.8244BD38  00000000.000001B8  
                       FFFFFFFF.8244BD40  00000000.00000050  
                       FFFFFFFF.8244BD48  00000000.00000210  UCB$N_RSID+00002
                       FFFFFFFF.8244BD50  00000000.00000000  
                       FFFFFFFF.8244BD58  00000000.00000000  
                       FFFFFFFF.8244BD60  FFFFFFFF.804045D0  SCH$GQ_IDLE_CPUS
                       FFFFFFFF.8244BD68  FFFFFFFF.8041A340  EXE$GL_FKWAITFL+00020
                       FFFFFFFF.8244BD70  00000000.00000250  UCB$T_MSGDATA+00034
                       FFFFFFFF.8244BD78  00000000.00000001  
CHF$IS_MCH_ARGS        FFFFFFFF.8244BD80  00000000.0000002B  
CHF$PH_MCH_FRAME       FFFFFFFF.8244BD88  FFFFFFFF.8244BFB0  
CHF$IS_MCH_DEPTH       FFFFFFFF.8244BD90  80000000.FFFFFFFD  G
CHF$PH_MCH_DADDR       FFFFFFFF.8244BD98  00000000.00001600  CTL$C_CLIDATASZ+00060
CHF$PH_MCH_ESF_ADDR    FFFFFFFF.8244BDA0  FFFFFFFF.8244BF40  
CHF$PH_MCH_SIG_ADDR    FFFFFFFF.8244BDA8  FFFFFFFF.8244BEE8  
CHF$IH_MCH_SAVR0       FFFFFFFF.8244BDB0  FFFFFFFF.8041FB00  SMP$RELEASEL+00640
CHF$IH_MCH_SAVR1       FFFFFFFF.8244BDB8  00000000.00000000  
CHF$IH_MCH_SAVR16      FFFFFFFF.8244BDC0  00000000.0000000D  
CHF$IH_MCH_SAVR17      FFFFFFFF.8244BDC8  0000FFF0.00007E04  
CHF$IH_MCH_SAVR18      FFFFFFFF.8244BDD0  00000000.00000000  
CHF$IH_MCH_SAVR19      FFFFFFFF.8244BDD8  00000000.00000001  
CHF$IH_MCH_SAVR20      FFFFFFFF.8244BDE0  00000000.00000000  
CHF$IH_MCH_SAVR21      FFFFFFFF.8244BDE8  FFFFFFFF.805AE4B6  SISR+0006E
CHF$IH_MCH_SAVR22      FFFFFFFF.8244BDF0  00000000.00000001  
CHF$IH_MCH_SAVR23      FFFFFFFF.8244BDF8  00000000.00000010  
CHF$IH_MCH_SAVR24      FFFFFFFF.8244BE00  00000000.00000008  
CHF$IH_MCH_SAVR25      FFFFFFFF.8244BE08  00000000.00000010  
CHF$IH_MCH_SAVR26      FFFFFFFF.8244BE10  00000000.00000001  
CHF$IH_MCH_SAVR27      FFFFFFFF.8244BE18  00000000.00000000  
CHF$IH_MCH_SAVR28      FFFFFFFF.8244BE20  FFFFFFFF.804045D0  SCH$GQ_IDLE_CPUS
                       FFFFFFFF.8244BE28  30000000.00000300  UCB$L_PI_SVA
                       FFFFFFFF.8244BE30  FFFFFFFF.80040F6C  EXE$REFLECT_C+00950
                       FFFFFFFF.8244BE38  18000000.00000300  UCB$L_PI_SVA
                       FFFFFFFF.8244BE40  FFFFFFFF.804267A0  EXE$CONTSIGNAL+00228
                       FFFFFFFF.8244BE48  00000000.7FFD00A8  PIO$GW_IIOIMPA
                       FFFFFFFF.8244BE50  00000003.00000000  
                       FFFFFFFF.8244BE58  FFFFFFFF.8003FC20  EXE$CONNECT_SERVICES_C+00920
                       FFFFFFFF.8244BE60  FFFFFFFF.8041FB00  SMP$RELEASEL+00640
                       FFFFFFFF.8244BE68  00000000.00000000  
                       FFFFFFFF.8244BE70  FFFFFFFF.8042CD50  SCH$WAIT_PROC+00060
                       FFFFFFFF.8244BE78  00000000.0000000D  
                       FFFFFFFF.8244BE80  0000FFF0.00007E04  
                       FFFFFFFF.8244BE88  00000000.00000000  
                       FFFFFFFF.8244BE90  00000000.00000001  
                       FFFFFFFF.8244BE98  00000000.00000000  
                       FFFFFFFF.8244BEA0  FFFFFFFF.805AE4B6  SISR+0006E
                       FFFFFFFF.8244BEA8  00000000.00000001  
                       FFFFFFFF.8244BEB0  00000000.00000010  
                       FFFFFFFF.8244BEB8  00000000.00000008  
                       FFFFFFFF.8244BEC0  00000000.00000010  
                       FFFFFFFF.8244BEC8  00000000.00000001  
                       FFFFFFFF.8244BED0  00000000.00000000  
                       FFFFFFFF.8244BED8  FFFFFFFF.804045D0  SCH$GQ_IDLE_CPUS
                       FFFFFFFF.8244BEE0  00000000.00000001  
CHF$L_SIG_ARGS         FFFFFFFF.8244BEE8  0000000C.00000005  
CHF$L_SIG_ARG1         FFFFFFFF.8244BEF0  FFFFFFFC.00010000  SYS$K_VERSION_08
                       FFFFFFFF.8244BEF8  00000300.FFFFFFFC  UCB$L_PI_SVA
                       FFFFFFFF.8244BF00  00000002.00000001  
                       FFFFFFFF.8244BF08  00000000.0000000C  
                       FFFFFFFF.8244BF10  00000000.00000000  
                       FFFFFFFF.8244BF18  00000000.FFFFFFFC  
                       FFFFFFFF.8244BF20  00000008.00000000  
                       FFFFFFFF.8244BF28  00000000.00000001  
                       FFFFFFFF.8244BF30  00000008.00000000  
                       FFFFFFFF.8244BF38  00000000.FFFFFFFC  
INTSTK$Q_R2            FFFFFFFF.8244BF40  FFFFFFFF.80404668  SCH$GL_ACTIVE_PRIORITY
INTSTK$Q_R3            FFFFFFFF.8244BF48  FFFFFFFF.8042F280  SCH$WAIT_KERNEL_MODE
INTSTK$Q_R4            FFFFFFFF.8244BF50  FFFFFFFF.80615F00  
INTSTK$Q_R5            FFFFFFFF.8244BF58  00000000.00000000  
INTSTK$Q_R6            FFFFFFFF.8244BF60  FFFFFFFF.805AE000  
INTSTK$Q_R7            FFFFFFFF.8244BF68  00000000.00000000  
INTSTK$Q_PC            FFFFFFFF.8244BF70  00000000.FFFFFFFC  
INTSTK$Q_PS            FFFFFFFF.8244BF78  30000000.00000300  UCB$L_PI_SVA
                       FFFFFFFF.8244BF80  FFFFFFFF.80404668  SCH$GL_ACTIVE_PRIORITY
                       FFFFFFFF.8244BF88  00000000.7FFD00A8  PIO$GW_IIOIMPA
                       FFFFFFFF.8244BF90  00000000.00000000  
                       FFFFFFFF.8244BF98  FFFFFFFF.8042CD50  SCH$WAIT_PROC+00060
                       FFFFFFFF.8244BFA0  00000000.00000044  
                       FFFFFFFF.8244BFA8  FFFFFFFF.80403C30  SMP$GL_FLAGS
Prev SP (8244BFB0) =>  FFFFFFFF.8244BFB0  FFFFFFFF.8042CD50  SCH$WAIT_PROC+00060
                       FFFFFFFF.8244BFB8  00000000.00000000  
                       FFFFFFFF.8244BFC0  FFFFFFFF.805EE040  
                       FFFFFFFF.8244BFC8  FFFFFFFF.8006DB54  PROCESS_MANAGEMENT_NPRO+0DB54
                       FFFFFFFF.8244BFD0  FFFFFFFF.80404668  SCH$GL_ACTIVE_PRIORITY
                       FFFFFFFF.8244BFD8  FFFFFFFF.80615F00  
                       FFFFFFFF.8244BFE0  FFFFFFFF.8041B220  SCH$RESOURCE_WAIT
                       FFFFFFFF.8244BFE8  00000000.00000044  
                       FFFFFFFF.8244BFF0  FFFFFFFF.80403C30  SMP$GL_FLAGS
                       FFFFFFFF.8244BFF8  00000000.7FF95E00

The SHOW STACK command displays a system stack. The data shown above the stack pointer may not be valid. Note that the mechanism array, signal array, and exception frame symbols displayed on the left will appear only for INVEXCEPTN, FATALEXCPT, UNXSIGNAL, and SSRVEXCEPT bugchecks.

Contents

Index

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OpenVMS Alpha System Analysis Tools Manual

SHOW SPINLOCKS

Format

SHOW SPINLOCKS {[name]|/ADDRESS=expression|/INDEX=expression} [/OWNED|/DYNAMIC|/STATIC] [{/BRIEF|/FULL}]

Parameter

name

Qualifiers

/ADDRESS=expression

/BRIEF

/DYNAMIC

/FULL

/INDEX=expression

/OWNED

/STATIC

Description

Examples

SHOW STACK

Format

SHOW STACK {range|/ALL|[/EXECUTIVE|/INTERRUPT|/KERNEL |/PHYSICAL|/SUPERVISOR|/SYSTEM|/USER]} {/LONG|/QUAD (d)}

Parameter

range

Qualifiers

/ALL

/EXECUTIVE

/INTERRUPT

/KERNEL

/LONG

/PHYSICAL

/QUAD

/SUPERVISOR

/SYSTEM

/USER

Description

Example

m:n	Range of addresses from m to n
m;n	Range of addresses starting at m and continuing for n bytes