Updated: 11 December 1998

VAX MACRO and Instruction Set Reference Manual

Chapter 10
10	VAX Vector Architecture
10.1	Introduction to VAX Vector Architecture
10.2	VAX Vector Architecture Registers
10.2.1	Vector Registers
10.2.2	Vector Control Registers
10.2.3	Internal Processor Registers
10.3	Vector Instruction Formats
10.3.1	Masked Operations
10.3.2	Exception Enable Bit
10.3.3	Modify Intent Bit
10.3.4	Register Specifier Fields
10.3.5	Vector Control Word Formats
10.3.6	Restrictions on Operand Specifier Usage
10.3.7	VAX Condition Codes
10.3.8	Illegal Vector Opcodes
10.4	Assembler Notation
10.5	Execution Model
10.5.1	Access Mode Restrictions
10.5.2	Scalar Context Switching
10.5.3	Overlapped Instruction Execution
10.5.3.1	Vector Chaining
10.5.3.2	Register Conflict
10.5.3.3	Dependencies Among Vector Results
10.6	Vector Processor Exceptions
10.6.1	Vector Memory Management Exception Handling
10.6.2	Vector Arithmetic Exceptions
10.6.3	Vector Processor Disabled
10.6.4	Handling Disabled Faults and Vector Context Switching
10.6.5	MFVP Exception Reporting Examples
10.7	Synchronization
10.7.1	Scalar/Vector Instruction Synchronization (SYNC)
10.7.2	Scalar/Vector Memory Synchronization
10.7.2.1	Memory Instruction Synchronization (MSYNC)
10.7.2.2	Memory Activity Completion Synchronization (VMAC)
10.7.3	Other Synchronization Between the Scalar and Vector Processors
10.7.4	Memory Synchronization Within the Vector Processor (VSYNC)
10.7.5	Required Use of Memory Synchronization Instructions
10.7.5.1	When VSYNC Is Not Required
10.8	Memory Management
10.9	Hardware Errors
10.10	Vector Memory Access Instructions
10.10.1	Alignment Considerations
10.10.2	Stride Considerations
10.10.3	Context of Address Specifiers
10.10.4	Access Mode
10.10.5	Memory Instructions
Command 193	VLD
Command 194	VGATH
Command 195	VST
Command 196	VSCAT
10.11	Vector Integer Instructions
Command 197	VADDL
Command 198	VCMPL
Command 199	VMULL
Command 200	VSUBL
10.12	Vector Logical and Shift Instructions
Command 201	VBIC, VBIS, and VXOR
Command 202	VSL
10.13	Vector Floating-Point Instructions
10.13.1	Vector Floating-Point Exception Conditions
10.13.2	Floating-Point Instructions
Command 203	VADD
Command 204	VCMP
Command 205	VVCVT
Command 206	VDIV
Command 207	VMUL
Command 208	VSUB
10.14	Vector Edit Instructions
Command 209	VMERGE
Command 210	IOTA
10.15	Miscellaneous Instructions
Command 211	MFVP
Command 212	MTVP
Command 213	VSYNC
Appendix A
Appendix A	ASCII Character Set
Appendix B
Appendix B	Hexadecimal/Decimal Conversion
B.1	Hexadecimal to Decimal
B.2	Decimal to Hexadecimal
B.3	Powers of 2 and 16
Appendix D
Appendix D	Permanent Symbol Table Defined for Use with VAX MACRO
Appendix E
Appendix E	Exceptions That May Occur During Instruction Execution
E.1	Arithmetic Traps and Faults
E.1.1	Integer Overflow Trap
E.1.2	Integer Divide-by-Zero Trap
E.1.3	Floating Overflow Trap
E.1.4	Divide-by-Zero Trap
E.1.5	Floating Underflow Trap
E.1.6	Decimal String Overflow Trap
E.1.7	Subscript-Range Trap
E.1.8	Floating Overflow Fault
E.1.9	Divide-by-Zero Floating Fault
E.1.10	Floating Underflow Fault
E.2	Memory Management Exceptions
E.2.1	Access Control Violation Fault
E.2.2	Translation Not Valid Fault
E.3	Exceptions Detected During Operand Reference
E.3.1	Reserved Addressing Mode Fault
E.3.2	Reserved Operand Exception
E.4	Exceptions Occurring as the Consequence of an Instruction
E.4.1	Reserved or Privileged Instruction Fault
E.4.2	Operand Reserved to Customers Fault
E.4.3	Instruction Emulation Exceptions
E.4.4	Compatibility Mode Exception
E.4.5	Change Mode Trap
E.4.6	Breakpoint Fault
E.5	Trace Fault
E.5.1	Trace Operation When Entering a Change Mode Instruction
E.5.2	Trace Operation Upon Return From Interrupt
E.5.3	Trace Operation After a BISPSW Instruction
E.5.4	Trace Operation After a CALLS or CALLG Instruction
E.6	Serious System Failures
E.6.1	Kernel Stack Not Valid Abort
E.6.2	Interrupt Stack Not Valid Halt
E.6.3	Machine Check Exception

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