[OpenVMS documentation]
[Site home] [Send comments] [Help with this site] [How to order documentation] [OpenVMS site] [Compaq site]
Updated: 11 December 1998

VAX MACRO and Instruction Set Reference Manual


Previous Contents Index

S
.SAVE_PSECT directive
SBWC (Subtract with Carry) instruction
SBZ field
Scalar/vector memory synchronization
SCANC (Scan Characters) instruction
Section name
    made available to debugger
Self-relative queue
Shift instruction
    vector
Shift operator
Short literal mode
    usage restricted in vector floating-point instructions
Should Be Zero
    See SBZ field
.SHOW directive
Signed byte storage directive (.SIGNED BYTE)
Signed word storage directive (.SIGNED_WORD)
.SIGNED_BYTE directive
.SIGNED_WORD directive
Significance indicator
SKPC (Skip Character) instruction
SOBGEQ (Subtract One and Branch Greater Than or Equal) instruction
SOBGTR (Subtract One and Branch Greater Than) instruction
Source statement
    See Statement
SPANC (Span Characters) instruction
Stack frame
Statement
    character set
    comment
    continuation of
    format
    label
    operand
    operator
Stride
    vector
String argument
String data type
    character
    leading separate numeric
    packed decimal
    trailing numeric
String instructions #1
String instructions #2
String operator
    in macro
SUBB2 (Subtract Byte 2 Operand) instruction
SUBB3 (Subtract Byte 3 Operand) instruction
Subconditional assembly block directive
    .IF_FALSE
    .IF_TRUE
    .IF_TRUE_FALSE
Subconditional assembly block directive (.IF_x)
SUBD2 (Subtract D_floating 2 Operand) instruction
SUBD3 (Subtract D_floating 3 Operand) instruction
SUBF2 (Subtract F_floating 2 Operand) instruction
SUBF3 (Subtract F_floating 3 Operand) instruction
SUBG2 (Subtract G_floating 2 Operand) instruction
SUBG3 (Subtract G_floating 3 Operand) instruction
SUBH2 (Subtract H_floating 2 Operand) instruction
SUBH3 (Subtract H_floating 3 Operand) instruction
SUBL2 (Subtract Long 2 Operand) instruction
SUBL3 (Subtract Long 3 Operand) instruction
SUBP4 (Subtract Packed 4 Operand) instruction
SUBP6 (Subtract Packed 6 Operand) instruction
.SUBTITLE directive
Subtitle listing control directive
    (.SUBTITLE)
SUBW2 (Subtract Word 2 Operand) instruction
SUBW3 (Subtract Word 3 Operand) instruction
Summary of OPCODES
    alphabetic order
    numeric order
SVPCTX (Save Process Context) instruction
Symbol
    cross-referencing #1
    cross-referencing #2
    determining value of
    external #1
    external #2
    global #1
    global #2
    global #3
    global #4
    global #5
    in operand field
    in operator field
    local
    macro name #1
    macro name #2
    made available to debugger
    permanent #1
    permanent #2
    register name #1
    register name #2
    suppressing
    transferral to VAX Symbolic Debugger
    undefined
    user-defined #1
    user-defined #2
Symbol attribute directive
    (.WEAK)
Symbol definition for shareable image
Symbol for shareable image directive (.TRANSFER)
SYNC (Scalar/Vector Instruction Synchronization) instruction #1
SYNC (Scalar/Vector Instruction Synchronization) instruction #2
SYNC (Scalar/Vector Instruction Synchronization) instruction #3
Synchronization
Synchronous memory management exception handling
System Control Block (SCB) vector
System failure
T
Tab stops
    in source statement
TB (Translation buffer)
    vector #1
    vector #2
    vector #3
    vector #4
    vector #5
    vector #6
    vector #7
TBIA (TB Invalidate All) instruction
TBIS (TB Invalidate Single) instruction
Term in MACRO statement
Textual operator
.TITLE directive
Title listing control directive
    (.TITLE)
Trace trap enable (T)
Traceback
Trailing numeric string
    data type
.TRANSFER directive
Translation buffer
    See TB
Trap
    arithmetic
    arithmetic type code
    change mode
    decimal
        string overflow
    decimal overflow
    divide by zero
    floating
        divide-by-zero
        overflow
        underflow
    integer
        divide-by-zero
        overflow
    integer overflow
    subscript-range
    trace
TSTB (Test Byte) instruction
TSTD (Test D_floating) instruction
TSTF (Test F_floating) instruction
TSTG (Test G_floating) instruction
TSTH (Test H_floating) instruction
TSTL (Test Long) instruction
TSTW (Test Word) instruction
U
Unary operator
UNDEFINED results
UNPREDICTABLE results
User-defined local label
    range
User-defined symbol #1
User-defined symbol #2
V
VADD (Vector Floating Add) instruction
VADDL (Vector Integer Add) instruction
VAER (Vector Arithmetic Exception Register)
Variable bit base address access type
Variable-length bit field
    bytes referenced
    data type
Variable-length bit field instructions
VAX architecture
    scalar
    vector
VAX condition codes
VBIC (Vector Bit Clear) instruction
VBIS (Vector Bit Set) instruction
VCMP (Vector Floating Compare) instruction
VCMPL (Vector Integer Compare) instruction
VCR (Vector Count Register) #1
VCR (Vector Count Register) #2
VCR (Vector Count Register) #3
VDIV (Vector Floating Divide) instruction
Vector address translation
Vector code
    assembling
Vector control word #1
Vector control word #2
Vector control word #3
    EXC (Exception Enable) bit #1
    EXC (Exception Enable) bit #2
    EXC (Exception Enable) bit #3
    EXC (Exception Enable) bit #4
    EXC (Exception Enable) bit #5
    EXC (Exception Enable) bit #6
    EXC (Exception Enable) bit #7
    EXC (Exception Enable) bit #8
    EXC (Exception Enable) bit #9
    EXC (Exception Enable) bit #10
    EXC (Exception Enable) bit #11
    EXC (Exception Enable) bit #12
    EXC (Exception Enable) bit #13
    EXC (Exception Enable) bit #14
    EXC (Exception Enable) bit #15
    EXC (Exception Enable) bit #16
    MI (Modify Intent) bit #1
    MI (Modify Intent) bit #2
    MI (Modify Intent) bit #3
    MI (Modify Intent) bit #4
    MI (Modify Intent) bit #5
    MOE (Masked Operations Enable) bit #1
    MOE (Masked Operations Enable) bit #2
    MOE (Masked Operations Enable) bit #3
    MTF (Match True/False) bit #1
    MTF (Match True/False) bit #2
    MTF (Match True/False) bit #3
    register specifier fields
Vector Count Register
    See VCR
Vector instruction
    decoding
    execution
    formats
Vector Length Register
    See VLR
Vector Logical Functions
Vector Mask Register
    See VMR
Vector memory
    access mode #1
    access mode #2
    accessing page tables
    alignment
    HALT considerations
    indicating intent to modify
    instructions
    management
        See Memory management
    required use of synchronization instructions
    scalar/vector synchronization of
    stride
Vector Memory Activity Check Register
    SeeVMAC
Vector opcode
    See Appendix D
Vector processor disabled #1
Vector processor disabled #2
Vector Processor Status Register
    See VPSR
Vector registers
Vector State Address Register
    See VSAR
VGATH (Gather Memory Data into Vector Register) instruction #1
VGATH (Gather Memory Data into Vector Register) instruction #2
VGATH (Gather Memory Data into Vector Register) instruction #3
Virtual address
Virtual-machine processor status longword (VMPSL)
VLD (Load Memory Data into Vector Register) instruction #1
VLD (Load Memory Data into Vector Register) instruction #2
VLD (Load Memory Data into Vector Register) instruction #3
VLD (Load Memory Data into Vector Register) instruction #4
VLR (Vector Length Register) #1
VLR (Vector Length Register) #2
VLR (Vector Length Register) #3
VMAC (Vector Memory Activity Check) Register #1
VMAC (Vector Memory Activity Check) Register #2
VMAC (Vector Memory Activity Check) Register #3
VMAC (Vector Memory Activity Check) Register #4
VMAC (Vector Memory Activity Check) Register #5
VMAC (Vector Memory Activity Check) Register #6
VMERGE (Vector Merge) instruction
VMPSL
    See Virtual-machine processor status longword
VMR (Vector Mask Register)
VMR (Vector Mask Register) #1
VMR (Vector Mask Register) #2
VMR (Vector Mask Register) #3
VMUL (Vector Floating Multiply) instruction
VMULL (Vector Integer Multiply) instruction
VPSR (Vector Processor Status Register) #1
VPSR (Vector Processor Status Register) #2
VPSR (Vector Processor Status Register) #3
VPSR (Vector Processor Status Register) #4
VPSR (Vector Processor Status Register) #5
    AEX (Arithmetic Exception) bit #1
    AEX (Arithmetic Exception) bit #2
    AEX (Arithmetic Exception) bit #3
    AEX (Arithmetic Exception) bit #4
    AEX (Arithmetic Exception) bit #5
    AEX (Arithmetic Exception) bit #6
    BSY (Busy) bit #1
    BSY (Busy) bit #2
    BSY (Busy) bit #3
    BSY (Busy) bit #4
    BSY (Busy) bit #5
    BSY (Busy) bit #6
    BSY (Busy) bit #7
    BSY (Busy) bit #8
    BSY (Busy) bit #9
    BSY (Busy) bit #10
    BSY (Busy) bit #11
    IMP (Implementation-Specific Hardware Error) bit
    IMP (Implementation-Specific Hardware Error) bit #1
    IMP (Implementation-Specific Hardware Error) bit #2
    IMP (Implementation-Specific Hardware Error) bit #3
    IMP (Implementation-Specific Hardware Error) bit #4
    IMP (Implementation-Specific Hardware Error) bit #5
    IMP (Implementation-Specific Hardware Error) bit #6
    IVO (Illegal Vector Opcode) bit #1
    IVO (Illegal Vector Opcode) bit #2
    IVO (Illegal Vector Opcode) bit #3
    IVO (Illegal Vector Opcode) bit #4
    IVO (Illegal Vector Opcode) bit #5
    IVO (Illegal Vector Opcode) bit #6
    MF (Memory Fault) bit #1
    MF (Memory Fault) bit #2
    MF (Memory Fault) bit #3
    MF (Memory Fault) bit #4
VPSR (Vector Processor Status Register)
    PMF (Pending Memory Fault) bit
VPSR (Vector Processor Status Register)
    PMF (Pending Memory Fault) bit #1
    PMF (Pending Memory Fault) bit #2
    PMF (Pending Memory Fault) bit #3
    PMF (Pending Memory Fault) bit #4
    RLD (State Reload) bit #1
    RLD (State Reload) bit #2
    RLD (State Reload) bit #3
    RST (State Reset) bit #1
    RST (State Reset) bit #2
    RST (State Reset) bit #3
    RST (State Reset) bit #4
    RST (State Reset) bit #5
    RST (State Reset) bit #6
    STS (State Store) bit #1
    STS (State Store) bit #2
    STS (State Store) bit #3
    VEN (Enable) bit #1
    VEN (Enable) bit #2
    VEN (Enable) bit #3
    VEN (Enable) bit #4
    VEN (Enable) bit #5
    VEN (Enable) bit #6
    VEN (Enable) bit #7
    VEN (Enable) bit #8
    VEN (Enable) bit #9
    VEN (Enable) bit #10
    VEN (Enable) bit #11
    VEN (Enable) bit #12
    VEN (Enable) bit #13
    VEN (Enable) bit #14
VSAR (Vector State Address Register)
VSCAT (Scatter Vector Register Data into Memory) instruction #1
VSCAT (Scatter Vector Register Data into Memory) instruction #2
VSCAT (Scatter Vector Register Data into Memory) instruction #3
VSCAT (Scatter Vector Register Data into Memory) instruction #4
VSL (Vector Shift Logical) instruction
VST (Store Vector Register Data into Memory) instruction #1
VST (Store Vector Register Data into Memory) instruction #2
VST (Store Vector Register Data into Memory) instruction #3
VST (Store Vector Register Data into Memory) instruction #4
VSUB (Vector Floating Subtract) instruction
VSUBL (Vector Integer Subtract) instruction
VSYNC (Synchronize Vector Memory Access) instruction #1
VSYNC (Synchronize Vector Memory Access) instruction #2
VSYNC (Synchronize Vector Memory Access) instruction #3
VSYNC (Synchronize Vector Memory Access) instruction #4
VTBIA (Vector TB Invalidate All) instruction #1
VTBIA (Vector TB Invalidate All) instruction #2
VTBIA (Vector TB Invalidate All) instruction #3
VTBIA (Vector TB Invalidate All) instruction #4
VTBIA (Vector TB Invalidate All) instruction #5
VTBIA (Vector TB Invalidate All) instruction #6
VVCVT (Vector Convert) instruction
VXOR (Vector Exclusive Or) instruction


Previous Next Contents Index

[Site home] [Send comments] [Help with this site] [How to order documentation] [OpenVMS site] [Compaq site]
[OpenVMS documentation]

Copyright © Compaq Computer Corporation 1998. All rights reserved.

Legal
4515PRO_INDEX_005.HTML